Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-9
ARCHITECTURE COMPATIBILITY
17.17 X87 FPU
This section addresses the issues that must be faced when porting floating-point
software designed to run on earlier IA-32 processors and math coprocessors to a
Pentium 4, Intel Xeon, P6 family, or Pentium processor with integrated x87 FPU. To
software, a Pentium 4, Intel Xeon, or P6 family processor looks very much like a
Pentium processor. Floating-point software which runs on a Pentium or Intel486 DX
processor, or on an Intel486 SX processor/Intel 487 SX math coprocessor system or
an Intel386 processor/Intel 387 math coprocessor system, will run with at most
minor modifications on a Pentium 4, Intel Xeon, or P6 family processor. To port code
directly from an Intel 286 processor/Intel 287 math coprocessor system or an
Intel 8086 processor/8087 math coprocessor system to a Pentium 4, Intel Xeon, P6
family, or Pentium processor, certain additional issues must be addressed.
In the following sections, the term “32-bit x87 FPUs” refers to the P6 family, Pentium,
and Intel486 DX processors, and to the Intel 487 SX and Intel 387 math coproces-
sors; the term “16-bit IA-32 math coprocessors” refers to the Intel 287 and 8087
math coprocessors.
17.17.1 Control Register CR0 Flags
The ET, NE, and MP flags in control register CR0 control the interface between the
integer unit of an IA-32 processor and either its internal x87 FPU or an external math
coprocessor. The effect of these flags in the various IA-32 processors are described in
the following paragraphs.
The ET (extension type) flag (bit 4 of the CR0 register) is used in the Intel386
processor to indicate whether the math coprocessor in the system is an Intel 287
math coprocessor (flag is clear) or an Intel 387 DX math coprocessor (flag is set).
This bit is hardwired to 1 in the P6 family, Pentium, and Intel486 processors.
The NE (Numeric Exception) flag (bit 5 of the CR0 register) is used in the P6 family,
Pentium, and Intel486 processors to determine whether unmasked floating-point
exceptions are reported internally through interrupt vector 16 (flag is set) or exter-
nally through an external interrupt (flag is clear). On a hardware reset, the NE flag is
initialized to 0, so software using the automatic internal error-reporting mechanism
must set this flag to 1. This flag is nonexistent on the Intel386 processor.
As on the Intel 286 and Intel386 processors, the MP (monitor coprocessor) flag (bit 1
of register CR0) determines whether the WAIT/FWAIT instructions or waiting-type
floating-point instructions trap when the context of the x87 FPU is different from that
of the currently-executing task. If the MP and TS flag are set, then a WAIT/FWAIT
instruction and waiting instructions will cause a device-not-available exception
(interrupt vector 7). The MP flag is used on the Intel 286 and Intel386 processors to
support the use of a WAIT/FWAIT instruction to wait on a device other than a math
coprocessor. The device reports its status through the BUSY# pin. Since the P6
family, Pentium, and Intel486 processors do not have such a pin, the MP flag has no
relevant use and should be set to 1 for normal operation.