Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-10 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.17.2 x87 FPU Status Word
This section identifies differences to the x87 FPU status word for the different IA-32
processors and math coprocessors, the reason for the differences, and their impact
on software.
17.17.2.1 Condition Code Flags (C0 through C3)
The following information pertains to differences in the use of the condition code
flags (C0 through C3) located in bits 8, 9, 10, and 14 of the x87 FPU status word.
After execution of an FINIT instruction or a hardware reset on a 32-bit x87 FPU, the
condition code flags are set to 0. The same operations on a 16-bit IA-32 math copro-
cessor leave these flags intact (they contain their prior value). This difference in
operation has no impact on software and provides a consistent state after reset.
Transcendental instruction results in the core range of the P6 family and Pentium
processors may differ from the Intel486 DX processor and Intel 487 SX math copro-
cessor by 2 to 3 units in the last place (ulps)—(see “Transcendental Instruction Accu-
racy” in Chapter 8, “Programming with the x87 FPU,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1). As a result, the value saved
in the C1 flag may also differ.
After an incomplete FPREM/FPREM1 instruction, the C0, C1, and C3 flags are set to 0
on the 32-bit x87 FPUs. After the same operation on a 16-bit IA-32 math copro-
cessor, these flags are left intact.
On the 32-bit x87 FPUs, the C2 flag serves as an incomplete flag for the FTAN instruc-
tion. On the 16-bit IA-32 math coprocessors, the C2 flag is undefined for the FPTAN
instruction. This difference has no impact on software, because Intel 287 or 8087
programs do not check C2 after an FPTAN instruction. The use of this flag on later
processors allows fast checking of operand range.
17.17.2.2 Stack Fault Flag
When unmasked stack overflow or underflow occurs on a 32-bit x87 FPU, the IE flag
(bit 0) and the SF flag (bit 6) of the x87 FPU status word are set to indicate a stack
fault and condition code flag C1 is set or cleared to indicate overflow or underflow,
respectively. When unmasked stack overflow or underflow occurs on a 16-bit IA-32
math coprocessor, only the IE flag is set. Bit 6 is reserved on these processors. The
addition of the SF flag on a 32-bit x87 FPU has no impact on software. Existing excep-
tion handlers need not change, but may be upgraded to take advantage of the addi-
tional information.
17.17.3 x87 FPU Control Word
Only affine closure is supported for infinity control on a 32-bit x87 FPU. The infinity
control flag (bit 12 of the x87 FPU control word) remains programmable on these