Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-11
ARCHITECTURE COMPATIBILITY
processors, but has no effect. This change was made to conform to the IEEE Stan-
dard 754 for Binary Floating-Point Arithmetic. On a 16-bit IA-32 math coprocessor,
both affine and projective closures are supported, as determined by the setting of bit
12. After a hardware reset, the default value of bit 12 is projective. Software that
requires projective infinity arithmetic may give different results.
17.17.4 x87 FPU Tag Word
When loading the tag word of a 32-bit x87 FPU, using an FLDENV, FRSTOR, or
FXRSTOR (Pentium III processor only) instruction, the processor examines the
incoming tag and classifies the location only as empty or non-empty. Thus, tag
values of 00, 01, and 10 are interpreted by the processor to indicate a non-empty
location. The tag value of 11 is interpreted by the processor to indicate an empty
location. Subsequent operations on a non-empty register always examine the value
in the register, not the value in its tag. The FSTENV, FSAVE, and FXSAVE (Pentium III
processor only) instructions examine the non-empty registers and put the correct
values in the tags before storing the tag word.
The corresponding tag for a 16-bit IA-32 math coprocessor is checked before each
register access to determine the class of operand in the register; the tag is updated
after every change to a register so that the tag always reflects the most recent status
of the register. Software can load a tag with a value that disagrees with the contents
of a register (for example, the register contains a valid value, but the tag says
special). Here, the 16-bit IA-32 math coprocessors honor the tag and do not examine
the register.
Software written to run on a 16-bit IA-32 math coprocessor may not operate
correctly on a 16-bit x87 FPU, if it uses the FLDENV, FRSTOR, or FXRSTOR instruc-
tions to change tags to values (other than to empty) that are different from actual
register contents.
The encoding in the tag word for the 32-bit x87 FPUs for unsupported data formats
(including pseudo-zero and unnormal) is special (10B), to comply with IEEE Standard
754. The encoding in the 16-bit IA-32 math coprocessors for pseudo-zero and
unnormal is valid (00B) and the encoding for other unsupported data formats is
special (10B). Code that recognizes the pseudo-zero or unnormal format as valid
must therefore be changed if it is ported to a 32-bit x87 FPU.
17.17.5 Data Types
This section discusses the differences of data types for the various x87 FPUs and
math coprocessors.
17.17.5.1 NaNs
The 32-bit x87 FPUs distinguish between signaling NaNs (SNaNs) and quiet NaNs
(QNaNs). These x87 FPUs only generate QNaNs and normally do not generate an