Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-12 Vol. 3A
ARCHITECTURE COMPATIBILITY
exception upon encountering a QNaN. An invalid-operation exception (#I) is gener-
ated only upon encountering a SNaN, except for the FCOM, FIST, and FBSTP instruc-
tions, which also generates an invalid-operation exceptions for a QNaNs. This
behavior matches IEEE Standard 754.
The 16-bit IA-32 math coprocessors only generate one kind of NaN (the equivalent of
a QNaN), but the raise an invalid-operation exception upon encountering any kind of
NaN.
When porting software written to run on a 16-bit IA-32 math coprocessor to a 32-bit
x87 FPU, uninitialized memory locations that contain QNaNs should be changed to
SNaNs to cause the x87 FPU or math coprocessor to fault when uninitialized memory
locations are referenced.
17.17.5.2 Pseudo-zero, Pseudo-NaN, Pseudo-infinity, and Unnormal
Formats
The 32-bit x87 FPUs neither generate nor support the pseudo-zero, pseudo-NaN,
pseudo-infinity, and unnormal formats. Whenever they encounter them in an arith-
metic operation, they raise an invalid-operation exception. The 16-bit IA-32 math
coprocessors define and support special handling for these formats. Support for
these formats was dropped to conform with IEEE Standard 754 for Binary Floating-
Point Arithmetic.
This change should not impact software ported from 16-bit IA-32 math coprocessors
to 32-bit x87 FPUs. The 32-bit x87 FPUs do not generate these formats, and there-
fore will not encounter them unless software explicitly loads them in the data regis-
ters. The only affect may be in how software handles the tags in the tag word (see
also: Section 17.17.4, “x87 FPU Tag Word”).
17.17.6 Floating-Point Exceptions
This section identifies the implementation differences in exception handling for
floating-point instructions in the various x87 FPUs and math coprocessors.
17.17.6.1 Denormal Operand Exception (#D)
When the denormal operand exception is masked, the 32-bit x87 FPUs automatically
normalize denormalized numbers when possible; whereas, the 16-bit IA-32 math
coprocessors return a denormal result. A program written to run on a 16-bit IA-32
math coprocessor that uses the denormal exception solely to normalize denormal-
ized operands is redundant when run on the 32-bit x87 FPUs. If such a program is run
on 32-bit x87 FPUs, performance can be improved by masking the denormal excep-
tion. Floating-point programs run faster when the FPU performs normalization of
denormalized operands.
The denormal operand exception is not raised for transcendental instructions and the
FXTRACT instruction on the 16-bit IA-32 math coprocessors. This exception is raised