Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-15
ARCHITECTURE COMPATIBILITY
caused the exception. For the Pentium and Intel486 processors, an unmasked
floating-point exception may cause the FERR# pin to be asserted either at the end of
the instruction causing the exception or immediately before execution of the next
floating-point instruction. (Note that the next floating-point instruction would not be
executed until the pending unmasked exception has been handled.) See Appendix D,
“Guidelines for Writing x87 FPU Extension Handlers,” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, for a complete description of
the required mechanism for handling floating-point exceptions using the MS-DOS
compatibility mode.
17.17.6.8 Invalid Operation Exception On Denormals
An invalid-operation exception is not generated on the 32-bit x87 FPUs upon encoun-
tering a denormal value when executing a FSQRT, FDIV, or FPREM instruction or upon
conversion to BCD or to integer. The operation proceeds by first normalizing the
value. On the 16-bit IA-32 math coprocessors, upon encountering this situation, the
invalid-operation exception is generated. This difference has no impact on existing
software. Software running on the 32-bit x87 FPUs continues to execute in cases
where the 16-bit IA-32 math coprocessors trap. The reason for this change was to
eliminate an exception from being raised.
17.17.6.9 Alignment Check Exceptions (#AC)
If alignment checking is enabled, a misaligned data operand on the P6 family,
Pentium, and Intel486 processors causes an alignment check exception (#AC) when
a program or procedure is running at privilege-level 3, except for the stack portion of
the FSAVE/FNSAVE, FXSAVE, FRSTOR, and FXRSTOR instructions.
17.17.6.10 Segment Not Present Exception During FLDENV
On the Intel486 processor, when a segment not present exception (#NP) occurs in
the middle of an FLDENV instruction, it can happen that part of the environment is
loaded and part not. In such cases, the FPU control word is left with a value of 007FH.
The P6 family and Pentium processors ensure the internal state is correct at all times
by attempting to read the first and last bytes of the environment before updating the
internal state.
17.17.6.11 Device Not Available Exception (#NM)
The device-not-available exception (#NM, interrupt 7) will occur in the P6 family,
Pentium, and Intel486 processors as described in Section 2.5, “Control Registers,”
Table 2-1, and Chapter 5, “Interrupt 7—Device Not Available Exception (#NM).”