Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-16 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.17.6.12 Coprocessor Segment Overrun Exception
The coprocessor segment overrun exception (interrupt 9) does not occur in the P6
family, Pentium, and Intel486 processors. In situations where the Intel 387 math
coprocessor would cause an interrupt 9, the P6 family, Pentium, and Intel486 proces-
sors simply abort the instruction. To avoid undetected segment overruns, it is recom-
mended that the floating-point save area be placed in the same page as the TSS. This
placement will prevent the FPU environment from being lost if a page fault occurs
during the execution of an FLDENV, FRSTOR, or FXRSTOR instruction while the oper-
ating system is performing a task switch.
17.17.6.13 General Protection Exception (#GP)
A general-protection exception (#GP, interrupt 13) occurs if the starting address of a
floating-point operand falls outside a segment’s size. An exception handler should be
included to report these programming errors.
17.17.6.14 Floating-Point Error Exception (#MF)
In real mode and protected mode (not including virtual-8086 mode), interrupt vector
16 must point to the floating-point exception handler. In virtual 8086 mode, the
virtual-8086 monitor can be programmed to accommodate a different location of the
interrupt vector for floating-point exceptions.
17.17.7 Changes to Floating-Point Instructions
This section identifies the differences in floating-point instructions for the various
Intel FPU and math coprocessor architectures, the reason for the differences, and
their impact on software.
17.17.7.1 FDIV, FPREM, and FSQRT Instructions
The 32-bit x87 FPUs support operations on denormalized operands and, when
detected, an underflow exception can occur, for compatibility with the IEEE Standard
754. The 16-bit IA-32 math coprocessors do not operate on denormalized operands
or return underflow results. Instead, they generate an invalid-operation exception
when they detect an underflow condition. An existing underflow exception handler
will require change only if it gives different treatment to different opcodes. Also, it is
possible that fewer invalid-operation exceptions will occur.
17.17.7.2 FSCALE Instruc t ion
With the 32-bit x87 FPUs, the range of the scaling operand is not restricted. If (0 < |
ST(1) < 1), the scaling factor is 0; therefore, ST(0) remains unchanged. If the
rounded result is not exact or if there was a loss of accuracy (masked underflow), the