Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-17
ARCHITECTURE COMPATIBILITY
precision exception is signaled. With the 16-bit IA-32 math coprocessors, the range
of the scaling operand is restricted. If (0 < | ST(1) | < 1), the result is undefined and
no exception is signaled. The impact of this difference on exiting software is that
different results are delivered on the 32-bit and 16-bit FPUs and math coprocessors
when (0 < | ST(1) | < 1).
17. 1 7. 7. 3 F PREM 1 In s t ru ct i on
The 32-bit x87 FPUs compute a partial remainder according to IEEE Standard 754.
This instruction does not exist on the 16-bit IA-32 math coprocessors. The avail-
ability of the FPREM1 instruction has is no impact on existing software.
17. 1 7. 7. 4 F PREM I nst ruc tio n
On the 32-bit x87 FPUs, the condition code flags C0, C3, C1 in the status word
correctly reflect the three low-order bits of the quotient following execution of the
FPREM instruction. On the 16-bit IA-32 math coprocessors, the quotient bits are
incorrect when performing a reduction of (64
N
+ M) when (N ≥ 1) and M is 1 or 2. This
difference does not affect existing software; software that works around the bug
should not be affected.
17.17.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions
When executing the FUCOM, FUCOMP, and FUCOMPP instructions, the 32-bit x87
FPUs perform unordered compare according to IEEE Standard 754. These instruc-
tions do not exist on the 16-bit IA-32 math coprocessors. The availability of these
new instructions has no impact on existing software.
17. 1 7. 7. 6 F PTA N I n str u ct ion
On the 32-bit x87 FPUs, the range of the operand for the FPTAN instruction is much
less restricted (| ST(0) | < 2
63
) than on earlier math coprocessors. The instruction
reduces the operand internally using an internal π/4 constant that is more accurate.
The range of the operand is restricted to (| ST(0) | < π/4) on the 16-bit IA-32 math
coprocessors; the operand must be reduced to this range using FPREM. This change
has no impact on existing software.
17. 1 7. 7. 7 Stac k Ove rfl ow
On the 32-bit x87 FPUs, if an FPU stack overflow occurs when the invalid-operation
exception is masked, the FPU returns the real, integer, or BCD-integer indefinite
value to the destination operand, depending on the instruction being executed. On
the 16-bit IA-32 math coprocessors, the original operand remains unchanged
following a stack overflow, but it is loaded into register ST(1). This difference has no
impact on existing software.