Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1
17-18 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.17.7.8 FSIN, FCOS, and FSINCOS Instructions
On the 32-bit x87 FPUs, these instructions perform three common trigonometric
functions. These instructions do not exist on the 16-bit IA-32 math coprocessors. The
availability of these instructions has no impact on existing software, but using them
provides a performance upgrade.
17.17.7.9 FPATAN Instruction
On the 32-bit x87 FPUs, the range of operands for the FPATAN instruction is unre-
stricted. On the 16-bit IA-32 math coprocessors, the absolute value of the operand in
register ST(0) must be smaller than the absolute value of the operand in register
ST(1). This difference has impact on existing software.
17.17.7.10 F2XM1 Instruction
The 32-bit x87 FPUs support a wider range of operands (–1 < ST (0) < + 1) for the
F2XM1 instruction. The supported operand range for the 16-bit IA-32 math coproces-
sors is (0 ≤ ST(0) ≤ 0.5). This difference has no impact on existing software.
17.17.7.11 FLD Instruction
On the 32-bit x87 FPUs, when using the FLD instruction to load an extended-real
value, a denormal-operand exception is not generated because the instruction is not
arithmetic. The 16-bit IA-32 math coprocessors do report a denormal-operand
exception in this situation. This difference does not affect existing software.
On the 32-bit x87 FPUs, loading a denormal value that is in single- or double-real
format causes the value to be converted to extended-real format. Loading a
denormal value on the 16-bit IA-32 math coprocessors causes the value to be
converted to an unnormal. If the next instruction is FXTRACT or FXAM, the 32-bit x87
FPUs will give a different result than the 16-bit IA-32 math coprocessors. This change
was made for IEEE Standard 754 compatibility.
On the 32-bit x87 FPUs, loading an SNaN that is in single- or double-real format
causes the FPU to generate an invalid-operation exception. The 16-bit IA-32 math
coprocessors do not raise an exception when loading a signaling NaN. The invalid-
operation exception handler for 16-bit math coprocessor software needs to be
updated to handle this condition when porting software to 32-bit FPUs. This change
was made for IEEE Standard 754 compatibility.
17.17.7.12 FXTRACT Instruction
On the 32-bit x87 FPUs, if the operand is 0 for the FXTRACT instruction, the divide-
by-zero exception is reported and –∞ is delivered to register ST(1). If the operand is
+∞, no exception is reported. If the operand is 0 on the 16-bit IA-32 math coproces-
sors, 0 is delivered to register ST(1) and no exception is reported. If the operand is