Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-19
ARCHITECTURE COMPATIBILITY
+∞, the invalid-operation exception is reported. These differences have no impact on
existing software. Software usually bypasses 0 and ∞. This change is due to the IEEE
Standard 754 recommendation to fully support the “logb” function.
17.17.7.13 Load Constant Instructions
On 32-bit x87 FPUs, rounding control is in effect for the load constant instructions.
Rounding control is not in effect for the 16-bit IA-32 math coprocessors. Results for
the FLDPI, FLDLN2, FLDLG2, and FLDL2E instructions are the same as for the 16-bit
IA-32 math coprocessors when rounding control is set to round to nearest or round
to +∞. They are the same for the FLDL2T instruction when rounding control is set to
round to nearest, round to –∞, or round to zero. Results are different from the 16-bit
IA-32 math coprocessors in the least significant bit of the mantissa if rounding
control is set to round to –∞ or round to 0 for the FLDPI, FLDLN2, FLDLG2, and
FLDL2E instructions; they are different for the FLDL2T instruction if round to +∞ is
specified. These changes were implemented for compatibility with IEEE Standard
754 for Floating-Point Arithmetic recommendations.
17.17.7.14 FSETPM Instruction
With the 32-bit x87 FPUs, the FSETPM instruction is treated as NOP (no operation).
This instruction informs the Intel 287 math coprocessor that the processor is in
protected mode. This change has no impact on existing software. The 32-bit x87
FPUs handle all addressing and exception-pointer information, whether in protected
mode or not.
17.17.7.15 FXAM Instruction
With the 32-bit x87 FPUs, if the FPU encounters an empty register when executing
the FXAM instruction, it not generate combinations of C0 through C3 equal to 1101 or
1111. The 16-bit IA-32 math coprocessors may generate these combinations, among
others. This difference has no impact on existing software; it provides a performance
upgrade to provide repeatable results.
17.17.7.16 FSAVE and FSTENV Instructions
With the 32-bit x87 FPUs, the address of a memory operand pointer stored by FSAVE
or FSTENV is undefined if the previous floating-point instruction did not refer to
memory
17.17.8 Transcendental Instructions
The floating-point results of the P6 family and Pentium processors for transcendental
instructions in the core range may differ from the Intel486 processors by about 2 or
3 ulps (see “Transcendental Instruction Accuracy” in Chapter 8, “Programming with