Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-20 Vol. 3A
ARCHITECTURE COMPATIBILITY
the x87 FPU,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1). Condition code flag C1 of the status word may differ as a result. The exact
threshold for underflow and overflow will vary by a few ulps. The P6 family and
Pentium processors’ results will have a worst case error of less than 1 ulp when
rounding to the nearest-even and less than 1.5 ulps when rounding in other modes.
The transcendental instructions are guaranteed to be monotonic, with respect to the
input operands, throughout the domain supported by the instruction.
Transcendental instructions may generate different results in the round-up flag (C1)
on the 32-bit x87 FPUs. The round-up flag is undefined for these instructions on the
16-bit IA-32 math coprocessors. This difference has no impact on existing software.
17.17.9 Obsolete Instructions
The 8087 math coprocessor instructions FENI and FDISI and the Intel 287 math
coprocessor instruction FSETPM are treated as integer NOP instructions in the 32-bit
x87 FPUs. If these opcodes are detected in the instruction stream, no specific opera-
tion is performed and no internal states are affected.
17.17.10 WAIT/FWAIT Prefix Differences
On the Intel486 processor, when a WAIT/FWAIT instruction precedes a floating-point
instruction (one which itself automatically synchronizes with the previous floating-
point instruction), the WAIT/FWAIT instruction is treated as a no-op. Pending
floating-point exceptions from a previous floating-point instruction are processed not
on the WAIT/FWAIT instruction but on the floating-point instruction following the
WAIT/FWAIT instruction. In such a case, the report of a floating-point exception may
appear one instruction later on the Intel486 processor than on a P6 family or Pentium
FPU, or on Intel 387 math coprocessor.
17.17.11 Operands Split Across Segments and/or Pages
On the P6 family, Pentium, and Intel486 processor FPUs, when the first half of an
operand to be written is inside a page or segment and the second half is outside, a
memory fault can cause the first half to be stored but not the second half. In this situ-
ation, the Intel 387 math coprocessor stores nothing.
17.17.12 FPU Instruction Synchronization
On the 32-bit x87 FPUs, all floating-point instructions are automatically synchro-
nized; that is, the processor automatically waits until the previous floating-point
instruction has completed before completing the next floating-point instruction. No
explicit WAIT/FWAIT instructions are required to assure this synchronization. For the
8087 math coprocessors, explicit waits are required before each floating-point