Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-21
ARCHITECTURE COMPATIBILITY
instruction to ensure synchronization. Although 8087 programs having explicit WAIT
instructions execute perfectly on the 32-bit IA-32 processors without reassembly,
these WAIT instructions are unnecessary.
17.18 SERIALIZING INSTRUCTIONS
Certain instructions have been defined to serialize instruction execution to ensure
that modifications to flags, registers and memory are completed before the next
instruction is executed (or in P6 family processor terminology “committed to machine
state”). Because the P6 family processors use branch-prediction and out-of-order
execution techniques to improve performance, instruction execution is not generally
serialized until the results of an executed instruction are committed to machine state
(see Chapter 2, “Intel® 64 and IA-32 Architectures,” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1).
As a result, at places in a program or task where it is critical to have execution
completed for all previous instructions before executing the next instruction (for
example, at a branch, at the end of a procedure, or in multiprocessor dependent
code), it is useful to add a serializing instruction. See Section 7.4, “Serializing
Instructions,” for more information on serializing instructions.
17.19 FPU AND MATH COPROCESSOR INITIALIZATION
Table 9-1 shows the states of the FPUs in the P6 family, Pentium, Intel486 processors
and of the Intel 387 math coprocessor and Intel 287 coprocessor following a power-
up, reset, or INIT, or following the execution of an FINIT/FNINIT instruction. The
following is some additional compatibility information concerning the initialization of
x87 FPUs and math coprocessors.
17.19.1 Intel
®
387 and Intel
®
287 Math Coprocessor Initialization
Following an Intel386 processor reset, the processor identifies its coprocessor type
(Intel
®
287 or Intel
®
387 DX math coprocessor) by sampling its ERROR# input some
time after the falling edge of RESET# signal and before execution of the first floating-
point instruction. The Intel 287 coprocessor keeps its ERROR# output in inactive
state after hardware reset; the Intel 387 coprocessor keeps its ERROR# output in
active state after hardware reset.
Upon hardware reset or execution of the FINIT/FNINIT instruction, the Intel 387
math coprocessor signals an error condition. The P6 family, Pentium, and Intel486
processors, like the Intel 287 coprocessor, do not.