Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-22 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.19.2 Intel486 SX Processor and Intel 487 SX Math Coprocessor
Initialization
When initializing an Intel486 SX processor and an Intel 487 SX math coprocessor,
the initialization routine should check the presence of the math coprocessor and
should set the FPU related flags (EM, MP, and NE) in control register CR0 accordingly
(see Section 2.5, “Control Registers,” for a complete description of these flags). Table
17-2 gives the recommended settings for these flags when the math coprocessor is
present. The FSTCW instruction will give a value of FFFFH for the Intel486 SX micro-
processor and 037FH for the Intel 487 SX math coprocessor.
The EM and MP flags in register CR0 are interpreted as shown in Table 17-3.
Following is an example code sequence to initialize the system and check for the
presence of Intel486 SX processor/Intel 487 SX math coprocessor.
fninit
fstcw mem_loc
mov ax, mem_loc
cmp ax, 037fh
jz Intel487_SX_Math_CoProcessor_present;ax=037fh
jmp Intel486_SX_microprocessor_present;ax=ffffh
Table 17-2. Recommended Values of the EM, MP, and NE Flags for Intel486 SX
Microprocessor/Intel 487 SX Math Coprocessor System
CR0 Flags Intel486 SX Processor Only Intel 487 SX Math Coprocessor Present
EM 1 0
MP 0 1
NE 1 0, for MS-DOS* systems
1, for user-defined exception handler
Table 17-3. EM and MP Flag Interpretation
EM MP Interpretation
0 0 Floating-point instructions are passed to FPU; WAIT/FWAIT
and other waiting-type instructions ignore TS.
0 1 Floating-point instructions are passed to FPU; WAIT/FWAIT
and other waiting-type instructions test TS.
1 0 Floating-point instructions trap to emulator; WAIT/FWAIT and
other waiting-type instructions ignore TS.
1 1 Floating-point instructions trap to emulator; WAIT/FWAIT and
other waiting-type instructions test TS.