Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-25
ARCHITECTURE COMPATIBILITY
17.21 MEMORY MANAGEMENT FACILITIES
The following sections describe the new memory management facilities available in
the various IA-32 processors and some compatibility differences.
17.21.1 New Memory Management Control Flags
The Pentium Pro processor introduced three new memory management features:
physical memory addressing extension, the global bit in page-table entries, and
general support for larger page sizes. These features are only available when oper-
ating in protected mode.
17.21.1.1 Physical Memory Addressing Extension
The new PAE (physical address extension) flag in control register CR4, bit 5, enables
4 additional address lines on the processor, allowing 36-bit physical addresses. This
option can only be used when paging is enabled, using a new page-table mechanism
provided to support the larger physical address range (see Section 3.8, “36-Bit Phys-
ical Addressing Using the PAE Paging Mechanism”).
17.21.1.2 Global Pages
The new PGE (page global enable) flag in control register CR4, bit 7, provides a
mechanism for preventing frequently used pages from being flushed from the trans-
lation lookaside buffer (TLB). When this flag is set, frequently used pages (such as
pages containing kernel procedures or common data tables) can be marked global by
setting the global flag in a page-directory or page-table entry.
On a task switch or a write to control register CR3 (which normally causes the TLBs
to be flushed), the entries in the TLB marked global are not flushed. Marking pages
global in this manner prevents unnecessary reloading of the TLB due to TLB misses
on frequently used pages. See Section 3.12, “Translation Lookaside Buffers (TLBs),”
for a detailed description of this mechanism.
17.21.1.3 Larger Page Sizes
The P6 family processors support large page sizes. This facility is enabled with the
PSE (page size extension) flag in control register CR4, bit 4. When this flag is set, the
processor supports either 4-KByte or 4-MByte page sizes when normal paging is used
and 4-KByte and 2-MByte page sizes when the physical address extension is used.
See Section 3.6.1, “Paging Options,” for more information about large page sizes.