Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-26 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.21.2 CD and NW Cache Control Flags
The CD and NW flags in control register CR0 were introduced in the Intel486
processor. In the P6 family and Pentium processors, these flags are used to imple-
ment a writeback strategy for the data cache; in the Intel486 processor, they imple-
ment a write-through strategy. See Table 10-5 for a comparison of these bits on the
P6 family, Pentium, and Intel486 processors. For complete information on caching,
see Chapter 10, “Memory Cache Control.”
17.21.3 Descriptor Types and Contents
Operating-system code that manages space in descriptor tables often contains an
invalid value in the access-rights field of descriptor-table entries to identify unused
entries. Access rights values of 80H and 00H remain invalid for the P6 family,
Pentium, Intel486, Intel386, and Intel 286 processors. Other values that were invalid
on the Intel 286 processor may be valid on the 32-bit processors because uses for
these bits have been defined.
17.21.4 Changes in Segment Descriptor Loads
On the Intel386 processor, loading a segment descriptor always causes a locked read
and write to set the accessed bit of the descriptor. On the P6 family, Pentium, and
Intel486 processors, the locked read and write occur only if the bit is not already set.
17.22 DEBUG FACILITIES
The P6 family and Pentium processors include extensions to the Intel486 processor
debugging support for breakpoints. To use the new breakpoint features, it is neces-
sary to set the DE flag in control register CR4.
17.22.1 Differences in Debug Register DR6
It is not possible to write a 1 to reserved bit 12 in debug status register DR6 on the
P6 family and Pentium processors; however, it is possible to write a 1 in this bit on the
Intel486 processor. See Table 9-1 for the different setting of this register following a
power-up or hardware reset.
17.22.2 Differences in Debug Register DR7
The P6 family and Pentium processors determines the type of breakpoint access by
the R/W0 through R/W3 fields in debug control register DR7 as follows:
00 Break on instruction execution only.