Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-27
ARCHITECTURE COMPATIBILITY
01 Break on data writes only.
10 Undefined if the DE flag in control register CR4 is cleared; break on I/O reads
or writes but not instruction fetches if the DE flag in control register CR4 is
set.
11 Break on data reads or writes but not instruction fetches.
On the P6 family and Pentium processors, reserved bits 11, 12, 14 and 15 are hard-
wired to 0. On the Intel486 processor, however, bit 12 can be set. See Table 9-1 for
the different settings of this register following a power-up or hardware reset.
17.22.3 Debug Registers DR4 and DR5
Although the DR4 and DR5 registers are documented as reserved, previous genera-
tions of processors aliased references to these registers to debug registers DR6 and
DR7, respectively. When debug extensions are not enabled (the DE flag in control
register CR4 is cleared), the P6 family and Pentium processors remain compatible
with existing software by allowing these aliased references. When debug extensions
are enabled (the DE flag is set), attempts to reference registers DR4 or DR5 will
result in an invalid-opcode exception (#UD).
17.23 RECOGNITION OF BREAKPOINTS
For the Pentium processor, it is recommended that debuggers execute the LGDT
instruction before returning to the program being debugged to ensure that break-
points are detected. This operation does not need to be performed on the P6 family,
Intel486, or Intel386 processors. Test Registers
The implementation of test registers on the Intel486 processor used for testing the
cache and TLB has been redesigned using MSRs on the P6 family and Pentium
processors. (Note that MSRs used for this function are different on the P6 family and
Pentium processors.) The MOV to and from test register instructions generate
invalid-opcode exceptions (#UD) on the P6 family processors.
17.24 EXCEPTIONS AND/OR EXCEPTION CONDITIONS
This section describes the new exceptions and exception conditions added to the 32-
bit IA-32 processors and implementation differences in existing exception handling.
See Chapter 5, “Interrupt and Exception Handling,” for a detailed description of the
IA-32 exceptions.
The Pentium III processor introduced new state with the XMM registers. Computations
involving data in these registers can produce exceptions. A new MXCSR
control/status register is used to determine which exception or exceptions have