Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-28 Vol. 3A
ARCHITECTURE COMPATIBILITY
occurred. When an exception associated with the XMM registers occurs, an interrupt
is generated.
• SIMD floating-point exception (#XF, interrupt 19) — New exceptions associated
with the SIMD floating-point registers and resulting computations.
No new exceptions were added with the Pentium Pro and Pentium II processors. The
set of available exceptions is the same as for the Pentium processor. However, the
following exception condition was added to the IA-32 with the Pentium Pro
processor:
• Machine-check exception (#MC, interrupt 18) — New exception conditions. Many
exception conditions have been added to the machine-check exception and a new
architecture has been added for handling and reporting on hardware errors. See
Chapter 14, “Machine-Check Architecture,” for a detailed description of the new
conditions.
The following exceptions and/or exception conditions were added to the IA-32 with
the Pentium processor:
• Machine-check exception (#MC, interrupt 18) — New exception. This exception
reports parity and other hardware errors. It is a model-specific exception and
may not be implemented or implemented differently in future processors. The
MCE flag in control register CR4 enables the machine-check exception. When this
bit is clear (which it is at reset), the processor inhibits generation of the machine-
check exception.
• General-protection exception (#GP, interrupt 13) — New exception condition
added. An attempt to write a 1 to a reserved bit position of a special register
causes a general-protection exception to be generated.
• Page-fault exception (#PF, interrupt 14) — New exception condition added. When
a 1 is detected in any of the reserved bit positions of a page-table entry, page-
directory entry, or page-directory pointer during address translation, a page-fault
exception is generated.
The following exception was added to the Intel486 processor:
• Alignment-check exception (#AC, interrupt 17) — New exception. Reports
unaligned memory references when alignment checking is being performed.
The following exceptions and/or exception conditions were added to the Intel386
processor:
• Divide-error exception (#DE, interrupt 0)
— Change in exception handling. Divide-error exceptions on the Intel386
processors always leave the saved CS:IP value pointing to the instruction that
failed. On the 8086 processor, the CS:IP value points to the next instruction.
— Change in exception handling. The Intel386 processors can generate the
largest negative number as a quotient for the IDIV instruction (80H and
8000H). The 8086 processor generates a divide-error exception instead.