Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-30 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.25.1 Interrupt Propagation Delay
External hardware interrupts may be recognized on different instruction boundaries
on the P6 family, Pentium, Intel486, and Intel386 processors, due to the superscaler
designs of the P6 family and Pentium processors. Therefore, the EIP pushed onto the
stack when servicing an interrupt may be different for the P6 family, Pentium,
Intel486, and Intel386 processors.
17.25.2 NMI Interrupts
After an NMI interrupt is recognized by the P6 family, Pentium, Intel486, Intel386,
and Intel 286 processors, the NMI interrupt is masked until the first IRET instruction
is executed, unlike the 8086 processor.
17.25.3 IDT Limit
The LIDT instruction can be used to set a limit on the size of the IDT. A double-fault
exception (#DF) is generated if an interrupt or exception attempts to read a vector
beyond the limit. Shutdown then occurs on the 32-bit IA-32 processors if the double-
fault handler vector is beyond the limit. (The 8086 processor does not have a shut-
down mode nor a limit.)
17.26 ADVANCED PROGRAMMABLE INTERRUPT
CONTROLLER (APIC)
The Advanced Programmable Interrupt Controller (APIC), referred to in this book as
the local APIC, was introduced into the IA-32 processors with the Pentium
processor (beginning with the 735/90 and 815/100 models) and is included in the
Pentium 4, Intel Xeon, and P6 family processors. The features and functions of the
local APIC are derived from the Intel 82489DX external APIC, which was used with
the Intel486 and early Pentium processors. Additional refinements of the local APIC
architecture were incorporated in the Pentium 4 and Intel Xeon processors.
17.26.1 Software Visible Differences Between the Local APIC and
the 82489DX
The following features in the local APIC features differ from those found in the
82489DX external APIC:
• When the local APIC is disabled by clearing the APIC software enable/disable flag
in the spurious-interrupt vector MSR, the state of its internal registers are
unaffected, except that the mask bits in the LVT are all set to block local
interrupts to the processor. Also, the local APIC ceases accepting IPIs except for