Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-31
ARCHITECTURE COMPATIBILITY
INIT, SMI, NMI, and start-up IPIs. In the 82489DX, when the local unit is
disabled, all the internal registers including the IRR, ISR and TMR are cleared and
the mask bits in the LVT are set. In this state, the 82489DX local unit will accept
only the reset deassert message.
• In the local APIC, NMI and INIT (except for INIT deassert) are always treated as
edge triggered interrupts, even if programmed otherwise. In the 82489DX, these
interrupts are always level triggered.
• In the local APIC, IPIs generated through the ICR are always treated as edge
triggered (except INIT Deassert). In the 82489DX, the ICR can be used to
generate either edge or level triggered IPIs.
• In the local APIC, the logical destination register supports 8 bits; in the 82489DX,
it supports 32 bits.
• In the local APIC, the APIC ID register is 4 bits wide; in the 82489DX, it is 8 bits
wide.
• The remote read delivery mode provided in the 82489DX and local APIC for
Pentium processors is not supported in the local APIC in the Pentium 4, Intel
Xeon, and P6 family processors.
• For the 82489DX, in the lowest priority delivery mode, all the target local APICs
specified by the destination field participate in the lowest priority arbitration. For
the local APIC, only those local APICs which have free interrupt slots will
participate in the lowest priority arbitration.
17.26.2 New Features Incorporated in the Local APIC for the P6
Family and Pentium Processors
The local APIC in the Pentium and P6 family processors have the following new
features not found in the 82489DX external APIC.
• Cluster addressing is supported in logical destination mode.
• Focus processor checking can be enabled/disabled.
• Interrupt input signal polarity can be programmed for the LINT0 and LINT1 pins.
• An SMI IPI is supported through the ICR and I/O redirection table.
• An error status register is incorporated into the LVT to log and report APIC errors.
In the P6 family processors, the local APIC incorporates an additional LVT register to
handle performance monitoring counter interrupts.