Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-32 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.26.3 New Features Incorporated in the Local APIC of the Pentium
4 and Intel Xeon Processors
The local APIC in the Pentium 4 and Intel Xeon processors has the following new
features not found in the P6 family and Pentium processors and in the 82489DX.
• The local APIC ID is extended to 8 bits.
• An thermal sensor register is incorporated into the LVT to handle thermal sensor
interrupts.
• The the ability to deliver lowest-priority interrupts to a focus processor is no
longer supported.
• The flat cluster logical destination mode is not supported.
17.27 TASK SWITCHING AND TSS
This section identifies the implementation differences of task switching, additions to
the TSS and the handling of TSSs and TSS segment selectors.
17.27.1 P6 Family and Pentium Processor TSS
When the virtual mode extensions are enabled (by setting the VME flag in control
register CR4), the TSS in the P6 family and Pentium processors contain an interrupt
redirection bit map, which is used in virtual-8086 mode to redirect interrupts back to
an 8086 program.
17.27.2 TSS Selector Writes
During task state saves, the Intel486 processor writes 2-byte segment selectors into
a 32-bit TSS, leaving the upper 16 bits undefined. For performance reasons, the P6
family and Pentium processors write 4-byte segment selectors into the TSS, with the
upper 2 bytes being 0. For compatibility reasons, code should not depend on the
value of the upper 16 bits of the selector in the TSS.
17.27.3 Order of Reads/Writes to the TSS
The order of reads and writes into the TSS is processor dependent. The P6 family and
Pentium processors may generate different page-fault addresses in control register
CR2 in the same TSS area than the Intel486 and Intel386 processors, if a TSS
crosses a page boundary (which is not recommended).