Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-33
ARCHITECTURE COMPATIBILITY
17.27.4 Using A 16-Bit TSS with 32-Bit Constructs
Task switches using 16-bit TSSs should be used only for pure 16-bit code. Any new
code written using 32-bit constructs (operands, addressing, or the upper word of the
EFLAGS register) should use only 32-bit TSSs. This is due to the fact that the 32-bit
processors do not save the upper 16 bits of EFLAGS to a 16-bit TSS. A task switch
back to a 16-bit task that was executing in virtual mode will never re-enable the
virtual mode, as this flag was not saved in the upper half of the EFLAGS value in the
TSS. Therefore, it is strongly recommended that any code using 32-bit constructs
use a 32-bit TSS to ensure correct behavior in a multitasking environment.
17.27.5 Differences in I/O Map Base Addresses
The Intel486 processor considers the TSS segment to be a 16-bit segment and
wraps around the 64K boundary. Any I/O accesses check for permission to access
this I/O address at the I/O base address plus the I/O offset. If the I/O map base
address exceeds the specified limit of 0DFFFH, an I/O access will wrap around and
obtain the permission for the I/O address at an incorrect location within the TSS. A
TSS limit violation does not occur in this situation on the Intel486 processor.
However, the P6 family and Pentium processors consider the TSS to be a 32-bit
segment and a limit violation occurs when the I/O base address plus the I/O offset is
greater than the TSS limit. By following the recommended specification for the I/O
base address to be less than 0DFFFH, the Intel486 processor will not wrap around
and access incorrect locations within the TSS for I/O port validation and the P6
family and Pentium processors will not experience general-protection exceptions
(#GP). Figure 17-1 demonstrates the different areas accessed by the Intel486 and
the P6 family and Pentium processors.