Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-34 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.28 CACHE MANAGEMENT
The P6 family processors include two levels of internal caches: L1 (level 1) and L2
(level 2). The L1 cache is divided into an instruction cache and a data cache; the L2
cache is a general-purpose cache. See Section 10.1, “Internal Caches, TLBs, and
Buffers,” for a description of these caches. (Note that although the Pentium II
processor L2 cache is physically located on a separate chip in the cassette, it is
considered an internal cache.)
The Pentium processor includes separate level 1 instruction and data caches. The
data cache supports a writeback (or alternatively write-through, on a line by line
basis) policy for memory updates.
The Intel486 processor includes a single level 1 cache for both instructions and data.
The meaning of the CD and NW flags in control register CR0 have been redefined for
the P6 family and Pentium processors. For these processors, the recommended value
(00B) enables writeback for the data cache of the Pentium processor and for the L1
data cache and L2 cache of the P6 family processors. In the Intel486 processor,
setting these flags to (00B) enables write-through for the cache.
External system hardware can force the Pentium processor to disable caching or to
use the write-through cache policy should that be required. In the P6 family proces-
sors, the MTRRs can be used to override the CD and NW flags (see Table 10-6).
Figure 17-1. I/O Map Base Address Differences
Intel486 Processor
FFFFH
I/O Map
Base Addres
FFFFH
FFFFH + 10H = FH
for I/O Validation
0H
FFFFH
FFFFH
I/O access at port 10H checks
0H
FFFFH + 10H = Outside Segment
for I/O Validation
bitmap at I/O address FFFFH + 10H,
which exceeds segment limit.
Wrap around does not occur,
general-protection exception (#GP)
I/O access at port 10H checks
bitmap at I/O map base address
FFFFH + 10H = offset 10H.
Offset FH from beginning of
TSS segment results because
P6 family and Pentium Processors
I/O Map
Base Addres
occurs. wraparound occurs.