Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-36 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.29 PAGING
This section identifies enhancements made to the paging mechanism and implemen-
tation differences in the paging mechanism for various IA-32 processors.
17.29.1 Large Pages
The Pentium processor extended the memory management/paging facilities of the
IA-32 to allow large (4 MBytes) pages sizes (see Section 3.6.1, “Paging Options”).
The first P6 family processor (the Pentium Pro processor) added a 2 MByte page size
to the IA-32 in conjunction with the physical address extension (PAE) feature (see
Section 3.8, “36-Bit Physical Addressing Using the PAE Paging Mechanism”).
The availability of large pages on any IA-32 processor can be determined via feature
bit 3 (PSE) of register EDX after the CPUID instruction has been execution with an
argument of 1. Intel processors that do not support the CPUID instruction do not
support page size enhancements. (See “CPUID—CPU Identification” in Chapter 3,
“Instruction Set Reference, A-M,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A, and AP-485, Intel Processor Identification and the
CPUID Instruction, for more information on the CPUID instruction.)
17.29.2 PCD and PWT Flags
The PCD and PWT flags were introduced to the IA-32 in the Intel486 processor to
control the caching of pages:
• PCD (page-level cache disable) flag—Controls caching on a page-by-page basis.
• PWT (page-level write-through) flag—Controls the write-through/writeback
caching policy on a page-by-page basis. Since the internal cache of the Intel486
processor is a write-through cache, it is not affected by the state of the PWT flag.
17.29.3 Enabling and Disabling Paging
Paging is enabled and disabled by loading a value into control register CR0 that modi-
fies the PG flag. For backward and forward compatibility with all IA-32 processors,
Intel recommends that the following operations be performed when enabling or
disabling paging:
1. Execute a MOV CR0, REG instruction to either set (enable paging) or clear
(disable paging) the PG flag.
2. Execute a near JMP instruction.
The sequence bounded by the MOV and JMP instructions should be identity mapped
(that is, the instructions should reside on a page whose linear and physical addresses
are identical).