Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-38 Vol. 3A
ARCHITECTURE COMPATIBILITY
17.30.2 Error Code Pushes
The Intel486 processor implements the error code pushed on the stack as a 16-bit
value. When pushed onto a 32-bit stack, the Intel486 processor only pushes 2 bytes
and updates ESP by 4. The P6 family and Pentium processors’ error code is a full 32
bits with the upper 16 bits set to zero. The P6 family and Pentium processors, there-
fore, push 4 bytes and update ESP by 4. Any code that relies on the state of the upper
16 bits may produce inconsistent results.
17.30.3 Fault Handling Effects on the Stack
During the handling of certain instructions, such as CALL and PUSHA, faults may
occur in different sequences for the different processors. For example, during far
calls, the Intel486 processor pushes the old CS and EIP before a possible branch fault
is resolved. A branch fault is a fault from a branch instruction occurring from a
segment limit or access rights violation. If a branch fault is taken, the Intel486 and
P6 family processors will have corrupted memory below the stack pointer. However,
the ESP register is backed up to make the instruction restartable. The P6 family
processors issue the branch before the pushes. Therefore, if a branch fault does
occur, these processors do not corrupt memory below the stack pointer. This imple-
mentation difference, however, does not constitute a compatibility problem, as only
values at or above the stack pointer are considered to be valid.
17.30.4 Interlevel RET/IRET From a 16-Bit Interrupt or Call Gate
If a call or interrupt is made from a 32-bit stack environment through a 16-bit gate,
only 16 bits of the old ESP can be pushed onto the stack. On the subsequent
RET/IRET, the 16-bit ESP is popped but the full 32-bit ESP is updated since control is
being resumed in a 32-bit stack environment. The Intel486 processor writes the SS
selector into the upper 16 bits of ESP. The P6 family and Pentium processors write
zeros into the upper 16 bits.
17.31 MIXING 16- AND 32-BIT SEGMENTS
The features of the 16-bit Intel 286 processor are an object-code compatible subset
of those of the 32-bit IA-32 processors. The D (default operation size) flag in
segment descriptors indicates whether the processor treats a code or data segment
as a 16-bit or 32-bit segment; the B (default stack size) flag in segment descriptors
indicates whether the processor treats a stack segment as a 16-bit or 32-bit
segment.
The segment descriptors used by the Intel 286 processor are supported by the 32-bit
IA-32 processors if the Intel-reserved word (highest word) of the descriptor is clear.
On the 32-bit IA-32 processors, this word includes the upper bits of the base address
and the segment limit.