Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-39
ARCHITECTURE COMPATIBILITY
The segment descriptors for data segments, code segments, local descriptor tables
(there are no descriptors for global descriptor tables), and task gates are the same
for the 16- and 32-bit processors. Other 16-bit descriptors (TSS segment, call gate,
interrupt gate, and trap gate) are supported by the 32-bit processors.
The 32-bit processors also have descriptors for TSS segments, call gates, interrupt
gates, and trap gates that support the 32-bit architecture. Both kinds of descriptors
can be used in the same system.
For those segment descriptors common to both 16- and 32-bit processors, clear bits
in the reserved word cause the 32-bit processors to interpret these descriptors
exactly as an Intel 286 processor does, that is:
• Base Address — The upper 8 bits of the 32-bit base address are clear, which limits
base addresses to 24 bits.
• Limit — The upper 4 bits of the limit field are clear, restricting the value of the
limit field to 64 KBytes.
• Granularity bit — The G (granularity) flag is clear, indicating the value of the
16-bit limit is interpreted in units of 1 byte.
• Big bit — In a data-segment descriptor, the B flag is clear in the segment
descriptor used by the 32-bit processors, indicating the segment is no larger than
64 KBytes.
• Default bit — In a code-segment descriptor, the D flag is clear, indicating 16-bit
addressing and operands are the default. In a stack-segment descriptor, the D
flag is clear, indicating use of the SP register (instead of the ESP register) and a
64-KByte maximum segment limit.
For information on mixing 16- and 32-bit code in applications, see Chapter 16,
“Mixing 16-Bit and 32-Bit Code.”
17.32 SEGMENT AND ADDRESS WRAPAROUND
This section discusses differences in segment and address wraparound between the
P6 family, Pentium, Intel486, Intel386, Intel 286, and 8086 processors.
17.32.1 Segment Wraparound
On the 8086 processor, an attempt to access a memory operand that crosses offset
65,535 or 0FFFFH or offset 0 (for example, moving a word to offset 65,535 or
pushing a word when the stack pointer is set to 1) causes the offset to wrap around
modulo 65,536 or 010000H. With the Intel 286 processor, any base and offset combi-
nation that addresses beyond 16 MBytes wraps around to the 1 MByte of the address
space. The P6 family, Pentium, Intel486, and Intel386 processors in real-address
mode generate an exception in these cases: