Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 17-43
ARCHITECTURE COMPATIBILITY
available MSRs. The new registers control the debug extensions, the performance
counters, the machine-check exception capability, the machine-check architecture,
and the MTRRs. These registers are accessible using the RDMSR and WRMSR instruc-
tions. Specific information on some of these new MSRs is provided in the following
sections. As with the Pentium processor MSR, the P6 family processor MSRs are not
guaranteed to be duplicated or provided in the next generation IA-32 processors.
17.36.2 RDMSR and WRMSR Instructions
The RDMSR (read model-specific register) and WRMSR (write model-specific
register) instructions recognize a much larger number of model-specific registers in
the P6 family processors. (See “RDMSR—Read from Model Specific Register” and
“WRMSR—Write to Model Specific Register” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volumes 2A & 2B for more information.)
17.36.3 Memory Type Range Registers
Memory type range registers (MTRRs) are a new feature introduced into the IA-32 in
the Pentium Pro processor. MTRRs allow the processor to optimize memory opera-
tions for different types of memory, such as RAM, ROM, frame buffer memory, and
memory-mapped I/O.
MTRRs are MSRs that contain an internal map of how physical address ranges are
mapped to various types of memory. The processor uses this internal memory map
to determine the cacheability of various physical memory locations and the optimal
method of accessing memory locations. For example, if a memory location is speci-
fied in an MTRR as write-through memory, the processor handles accesses to this
location as follows. It reads data from that location in lines and caches the read data
or maps all writes to that location to the bus and updates the cache to maintain cache
coherency. In mapping the physical address space with MTRRs, the processor recog-
nizes five types of memory: uncacheable (UC), uncacheable, speculatable, write-
combining (USWC), write-through (WT), write-protected (WP), and writeback (WB).
Earlier IA-32 processors (such as the Intel486 and Pentium processors) used the
KEN# (cache enable) pin and external logic to maintain an external memory map and
signal cacheable accesses to the processor. The MTRR mechanism simplifies hard-
ware designs by eliminating the KEN# pin and the external logic required to drive it.
See Chapter 9, “Processor Management and Initialization,” and Appendix B, “Model-
Specific Registers (MSRs),” for more information on the MTRRs.
17.36.4 Machine-Check Exception and Architecture
The Pentium processor introduced a new exception called the machine-check excep-
tion (#MC, interrupt 18). This exception is used to detect hardware-related errors,
such as a parity error on a read cycle.