Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

17-44 Vol. 3A
ARCHITECTURE COMPATIBILITY
The P6 family processors extend the types of errors that can be detected and that
generate a machine-check exception. It also provides a new machine-check architec-
ture for recording information about a machine-check error and provides extended
recovery capability.
The machine-check architecture provides several banks of reporting registers for
recording machine-check errors. Each bank of registers is associated with a specific
hardware unit in the processor. The primary focus of the machine checks is on bus
and interconnect operations; however, checks are also made of translation lookaside
buffer (TLB) and cache operations.
The machine-check architecture can correct some errors automatically and allow for
reliable restart of instruction execution. It also collects sufficient information for soft-
ware to use in correcting other machine errors not corrected by hardware.
See Chapter 14, “Machine-Check Architecture,” for more information on the
machine-check exception and the machine-check architecture.
17.36.5 Performance-Monitoring Counters
The P6 family and Pentium processors provide two performance-monitoring counters
for use in monitoring internal hardware operations. These counters are event
counters that can be programmed to count a variety of different types of events,
such as the number of instructions decoded, number of interrupts received, or
number of cache loads. Appendix A, “Performance-Monitoring Events,” lists all the
events that can be counted (Table A-14 for the P6 family processors and Table A-15
for the Pentium processors). The counters are set up, started, and stopped using two
MSRs and the RDMSR and WRMSR instructions. For the P6 family processors, the
current count for a particular counter can be read using the new RDPMC instruction.
The performance-monitoring counters are useful for debugging programs, optimizing
code, diagnosing system failures, or refining hardware designs. See Chapter 18,
“Debugging and Performance Monitoring,” for more information on these counters.
17.37 TWO WAYS TO RUN INTEL 286 PROCESSOR TASKS
When porting 16-bit programs to run on 32-bit IA-32 processors, there are two
approaches to consider:
• Porting an entire 16-bit software system to a 32-bit processor, complete with the
old operating system, loader, and system builder. Here, all tasks will have 16-bit
TSSs. The 32-bit processor is being used as if it were a faster version of the 16-bit
processor.
• Porting selected 16-bit applications to run in a 32-bit processor environment with
a 32-bit operating system, loader, and system builder. Here, the TSSs used to
represent 286 tasks should be changed to 32-bit TSSs. It is possible to mix 16
and 32-bit TSSs, but the benefits are small and the problems are great. All tasks