Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 2-21
SYSTEM ARCHITECTURE OVERVIEW
If the TS flag is set and the EM flag (bit 2 of CR0) is clear, a device-not-
available exception (#NM) is raised prior to the execution of any x87
FPU/MMX/SSE/ SSE2/SSE3 instruction; with the exception of PAUSE,
PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH. See the
paragraph below for the special case of the WAIT/FWAIT instructions.
If the TS flag is set and the MP flag (bit 1 of CR0) and EM flag are clear, an
#NM exception is not raised prior to the execution of an x87 FPU
WAIT/FWAIT instruction.
If the EM flag is set, the setting of the TS flag has no affect on the
execution of x87 FPU/MMX/SSE/SSE2/SSE3 instructions.
Table 2-1 shows the actions taken when the processor encounters an x87
FPU instruction based on the settings of the TS, EM, and MP flags. Table 11-1
and 12-1 show the actions taken when the processor encounters an
MMX/SSE/SSE2/SSE3 instruction.
The processor does not automatically save the context of the x87 FPU, XMM,
and MXCSR registers on a task switch. Instead, it sets the TS flag, which
causes the processor to raise an #NM exception whenever it encounters an
x87 FPU/MMX/SSE /SSE2/SSE3 instruction in the instruction stream for the
new task (with the exception of the instructions listed above).
The fault handler for the #NM exception can then be used to clear the TS flag (with
the CLTS instruction) and save the context of the x87 FPU, XMM, and MXCSR regis-
ters. If the task never encounters an x87 FPU/MMX/SSE/SSE2/SSE3 instruction; the
x87 FPU/MMX/SSE/SSE2/ SSE3 context is never saved.
EM Emulation (bit 2 of CR0) — Indicates that the processor does not have an
internal or external x87 FPU when set; indicates an x87 FPU is present when
Table 2-1. Action Taken By x87 FPU Instructions for Different
Combinations of EM, MP, and TS
CR0 Flags x87 FPU Instruction Type
EM MP TS Floating-Point WAIT/FWAIT
0 0 0 Execute Execute.
0 0 1 #NM Exception Execute.
0 1 0 Execute Execute.
0 1 1 #NM Exception #NM exception.
1 0 0 #NM Exception Execute.
1 0 1 #NM Exception Execute.
1 1 0 #NM Exception Execute.
1 1 1 #NM Exception #NM exception.