Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 2-23
SYSTEM ARCHITECTURE OVERVIEW
PWT Page-level Writes Transparent (bit 3 of CR3) — Controls the write-
through or write-back caching policy of the current page directory. When the
PWT flag is set, write-through caching is enabled; when the flag is clear,
write-back caching is enabled. This flag affects only internal caches (both L1
and L2, when present). The processor ignores this flag if paging is not used
(the PG flag in register CR0 is clear) or the CD (cache disable) flag in CR0 is
set.
See also: Section 10.5, “Cache Control” (for more information about the use
of this flag), and Section 3.7.6, “Page-Directory and Page-Table Entries” (for
a description of a companion PCD flag in the page-directory and page-table
entries).
VME Virtual-8086 Mode Extensions (bit 0 of CR4) — Enables interrupt- and
exception-handling extensions in virtual-8086 mode when set; disables the
extensions when clear. Use of the virtual mode extensions can improve the
performance of virtual-8086 applications by eliminating the overhead of
calling the virtual-8086 monitor to handle interrupts and exceptions that
occur while executing an 8086 program and, instead, redirecting the inter-
rupts and exceptions back to the 8086 program’s handlers. It also provides
hardware support for a virtual interrupt flag (VIF) to improve reliability of
running 8086 programs in multitasking and multiple-processor environ-
ments.
See also: Section 15.3, “Interrupt and Exception Handling in Virtual-8086
Mode.”
PVI Protected-Mode Virtual Interrupts (bit 1 of CR4) — Enables hardware
support for a virtual interrupt flag (VIF) in protected mode when set; disables
the VIF flag in protected mode when clear.
See also: Section 15.4, “Protected-Mode Virtual Interrupts.”
TSD Time Stamp Disable (bit 2 of CR4) — Restricts the execution of the
RDTSC instruction to procedures running at privilege level 0 when set; allows
RDTSC instruction to be executed at any privilege level when clear.
DE Debugging Extensions (bit 3 of CR4) — References to debug registers
DR4 and DR5 cause an undefined opcode (#UD) exception to be generated
when set; when clear, processor aliases references to registers DR4 and DR5
for compatibility with software written to run on earlier IA-32 processors.
See also: Section 18.2.2, “Debug Registers DR4 and DR5.”
PSE Page Size Extensions (bit 4 of CR4) — Enables 4-MByte pages when set;
restricts pages to 4 KBytes when clear.
See also: Section 3.6.1, “Paging Options.”