Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

2-24 Vol. 3A
SYSTEM ARCHITECTURE OVERVIEW
PAE Physical Address Extension (bit 5 of CR4) — When set, enables paging
mechanism to reference greater-or-equal-than-36-bit physical addresses.
When clear, restricts physical addresses to 32 bits. PAE must be enabled to
enable IA-32e mode operation. Enabling and disabling IA-32e mode opera-
tion also requires modifying CR4.PAE.
See also: Section 3.8, “36-Bit Physical Addressing Using the PAE Paging
Mechanism.”
MCE Machine-Check Enable (bit 6 of CR4) — Enables the machine-check
exception when set; disables the machine-check exception when clear.
See also: Chapter 14, “Machine-Check Architecture.”
PGE Page Global Enable (bit 7 of CR4) — (Introduced in the P6 family proces-
sors.) Enables the global page feature when set; disables the global page
feature when clear. The global page feature allows frequently used or shared
pages to be marked as global to all users (done with the global flag, bit 8, in
a page-directory or page-table entry). Global pages are not flushed from the
translation-lookaside buffer (TLB) on a task switch or a write to register CR3.
When enabling the global page feature, paging must be enabled (by setting
the PG flag in control register CR0) before the PGE flag is set. Reversing this
sequence may affect program correctness, and processor performance will
be impacted.
See also: Section 3.12, “Translation Lookaside Buffers (TLBs).”
PCE Performance-Monitoring Counter Enable (bit 8 of CR4) — Enables
execution of the RDPMC instruction for programs or procedures running at
any protection level when set; RDPMC instruction can be executed only at
protection level 0 when clear.
OSFXSR
Operating System Support for FXSAVE and FXRSTOR instructions
(bit 9 of CR4) — When set, this flag: (1) indicates to software that the oper-
ating system supports the use of the FXSAVE and FXRSTOR instructions, (2)
enables the FXSAVE and FXRSTOR instructions to save and restore the
contents of the XMM and MXCSR registers along with the contents of the x87
FPU and MMX registers, and (3) enables the processor to execute
SSE/SSE2/SSE3 instructions, with the exception of the PAUSE, PREFETCHh,
SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH.
If this flag is clear, the FXSAVE and FXRSTOR instructions will save and
restore the contents of the x87 FPU and MMX instructions, but they may not
save and restore the contents of the XMM and MXCSR registers. Also, the
processor will generate an invalid opcode exception (#UD) if it attempts to
execute any SSE/SSE2/SSE3 instruction, with the exception of PAUSE,
PREFETCHh, SFENCE, LFENCE, MFENCE, MOVNTI, and CLFLUSH. The oper-
ating system or executive must explicitly set this flag.