Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 2-25
SYSTEM ARCHITECTURE OVERVIEW
NOTE
CPUID feature flags FXSR, SSE, SSE2, and SSE3 indicate avail-
ability of the FXSAVE/FXRESTOR instructions, SSE extensions,
SSE2 extensions, and SSE3 extensions respectively. The
OSFXSR bit provides operating system software with a means of
enabling these features and indicating that the operating system
supports the features.
OSXMMEXCPT
Operating System Support for Unmasked SIMD Floating-Point Excep-
tions (bit 10 of CR4) — When set, indicates that the operating system
supports the handling of unmasked SIMD floating-point exceptions through
an exception handler that is invoked when a SIMD floating-point exception
(#XF) is generated. SIMD floating-point exceptions are only generated by
SSE/SSE2/SSE3 SIMD floating-point instructions.
The operating system or executive must explicitly set this flag. If this flag is
not set, the processor will generate an invalid opcode exception (#UD)
whenever it detects an unmasked SIMD floating-point exception.
XMXE
VMX-Enable Bit (bit 13 of CR4) — Enables VMX operation when set. See
Chapter 19, “Introduction to Virtual-Machine Extensions.”
TPL Task Priority Level (bit 3:0 of CR8) — This sets the threshold value corre-
sponding to the highest-priority interrupt to be blocked. A value of 0 means
all interrupts are enabled. This field is available in 64-bit mode. A value of 15
means all interrupts will be disabled.
2.5.1 CPUID Qualification of Control Register Flags
The VME, PVI, TSD, DE, PSE, PAE, MCE, PGE, PCE, OSFXSR, and OSXMMEXCPT flags
in control register CR4 are model specific. All of these flags (except the PCE flag) can
be qualified with the CPUID instruction to determine if they are implemented on the
processor before they are used.
The CR8 register is available on processors that support Intel 64 architecture.
2.6 SYSTEM INSTRUCTION SUMMARY
System instructions handle system-level functions such as loading system registers,
managing the cache, managing interrupts, or setting up the debug registers. Many of
these instructions can be executed only by operating-system or executive proce-
dures (that is, procedures running at privilege level 0). Others can be executed at
any privilege level and are thus available to application programs.