Intel 64 and IA-32 Architectures Software Developers Manual Volume 3A, System Programming Guide, Part 1

Vol. 3A 2-27
SYSTEM ARCHITECTURE OVERVIEW
2.6.1 Loading and Storing System Registers
The GDTR, LDTR, IDTR, and TR registers each have a load and store instruction for
loading data into and storing data from the register:
• LGDT (Load GDTR Register) — Loads the GDT base address and limit from
memory into the GDTR register.
• SGDT (Store GDTR Register) — Stores the GDT base address and limit from
the GDTR register into memory.
• LIDT (Load IDTR Register) — Loads the IDT base address and limit from
memory into the IDTR register.
• SIDT (Load IDTR Register — Stores the IDT base address and limit from the
IDTR register into memory.
• LLDT (Load LDT Register) — Loads the LDT segment selector and segment
descriptor from memory into the LDTR. (The segment selector operand can also
be located in a general-purpose register.)
• SLDT (Store LDT Register) — Stores the LDT segment selector from the LDTR
register into memory or a general-purpose register.
• LTR (Load Task Register) — Loads segment selector and segment descriptor
for a TSS from memory into the task register. (The segment selector operand can
also be located in a general-purpose register.)
• STR (Store Task Register) — Stores the segment selector for the current task
TSS from the task register into memory or a general-purpose register.
The LMSW (load machine status word) and SMSW (store machine status word)
instructions operate on bits 0 through 15 of control register CR0. These instructions
are provided for compatibility with the 16-bit Intel 286 processor. Programs written
RDPMC
4
Read Performance-Monitoring
Counter
Yes Yes
2
RDTSC
3
Read Time-Stamp Counter Yes Yes
2
NOTES:
1. Useful to application programs running at a CPL of 1 or 2.
2. The TSD and PCE flags in control register CR4 control access to these instructions by application
programs running at a CPL of 3.
3. These instructions were introduced into the IA-32 Architecture with the Pentium processor.
4. This instruction was introduced into the IA-32 Architecture with the Pentium Pro processor and
the Pentium processor with MMX technology.
5. This instruction is not supported in 64-bit mode.
Table 2-2. Summary of System Instructions (Contd.)
Instruction Description
Useful to
Application?
Protected from
Application?