Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

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DEBUGGING AND PERFORMANCE MONITORING
occurrence of the PEBS event that caused the counter to overflow. When the
state information has been logged, the counter is automatically reset to a
preselected value, and event counting begins again. This feature is available only
for a subset of the Pentium 4 and Intel Xeon processors’ performance events.
NOTES
DS save area and recording mechanism is not available in the SMM.
The feature is disabled on transition to the SMM mode. Similarly DS
recording is disabled on the generation of a machine check exception
and is cleared on processor RESET and INIT. DS recording is available
in real address mode.
The BTS and PEBS facilities may not be available on all processors.
The availability of these facilities is indicated by the
BTS_UNAVAILABLE and PEBS_UNAVAILABLE flags, respectively, in
the IA32_MISC_ENABLE MSR (see Appendix B).
The DS save area is divided into three parts (see Figure 18-38): buffer management
area, branch trace store (BTS) buffer, and PEBS buffer. The buffer management area
is used to define the location and size of the BTS and PEBS buffers. The processor
then uses the buffer management area to keep track of the branch and/or PEBS
records in their respective buffers and to record the performance counter reset value.
The linear address of the first byte of the DS buffer management area is specified
with the IA32_DS_AREA MSR.
The fields in the buffer management area are as follows:
• BTS buffer base — Linear address of the first byte of the BTS buffer. This
address should point to a natural doubleword boundary.
• BTS index — Linear address of the first byte of the next BTS record to be written
to. Initially, this address should be the same as the address in the BTS buffer
base field.
• BTS absolute maximum — Linear address of the next byte past the end of the
BTS buffer. This address should be a multiple of the BTS record size (12 bytes)
plus 1.
• BTS interrupt threshold — Linear address of the BTS record on which an
interrupt is to be generated. This address must point to an offset from the BTS
buffer base that is a multiple of the BTS record size. Also, it must be several
records short of the BTS absolute maximum address to allow a pending interrupt
to be handled prior to processor writing the BTS absolute maximum record.
• PEBS buffer base — Linear address of the first byte of the PEBS buffer. This
address should point to a natural doubleword boundary.
• PEBS index — Linear address of the first byte of the next PEBS record to be
written to. Initially, this address should be the same as the address in the PEBS
buffer base field.