Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-104 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
3. Match the CCCR Select value and ESCR name in Table A-9 to a value listed in
Table 18-26; select a CCCR and performance counter.
4. Set up an ESCR for the specific event or events to be counted and the privilege
levels at which the are to be counted.
5. Set up the CCCR for the performance counter by selecting the ESCR and the
desired event filters.
6. Set up the CCCR for optional cascading of event counts, so that when the
selected counter overflows its alternate counter starts.
7. Set up the CCCR to generate an optional performance monitor interrupt (PMI)
when the counter overflows. If PMI generation is enabled, the local APIC must be
set up to deliver the interrupt to the processor and a handler for the interrupt
must be in place.
8. Enable the counter to begin counting.
18.18.6.1 Selecting Events to Count
Table A-10 in Appendix A lists a set of at-retirement events for the Pentium 4 and
Intel Xeon processors. For each event listed in Table A-10, setup information is
provided. Table 18-27 gives an example of one of the events.
Table 18-27. Event Example
Event Name Event Parameters Parameter Value Description
branch_retired Counts the retirement of a branch.
Specify one or more mask bits to
select any combination of branch
taken, not-taken, predicted and
mispredicted.
ESCR restrictions MSR_CRU_ESCR2
MSR_CRU_ESCR3
See Table 15-3 for the addresses of
the ESCR MSRs
Counter numbers
per ESCR
ESCR2: 12, 13, 16
ESCR3: 14, 15, 17
The counter numbers associated
with each ESCR are provided. The
performance counters and
corresponding CCCRs can be obtained
from Table 15-3.
ESCR Event Select 06H ESCR[31:25]
ESCR Event Mask
Bit 0: MMNP
1: MMNM
2: MMTP
3: MMTM
ESCR[24:9],
Branch Not-taken Predicted,
Branch Not-taken Mispredicted,
Branch Taken Predicted,
Branch Taken Mispredicted.
CCCR Select 05H CCCR[15:13]