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Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

ManualsBrandsIntel ManualsOtherIntel Pentium 4 Processor 2.80 GHz, 512K Cache, 533 MHz FSB
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Table Of Contents
18-106 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
to be absolutely accurate and should be used as a relative guide for
tuning. Known discrepancies are documented where applicable.
The following procedure shows how to set up a performance counter for basic
counting; that is, the counter is set up to count a specified event indefinitely, wrap-
ping around whenever it reaches its maximum count. This procedure is continued
through the following four sections.
Using information in Table A-9, Appendix A, an event to be counted can be selected
as follows:
1. Select the event to be counted.
2. Select the ESCR to be used to select events to be counted from the ESCRs field.
3. Select the number of the counter to be used to count the event from the Counter
Numbers Per ESCR field.
4. Determine the name of the counter and the CCCR associated with the counter,
and determine the MSR addresses of the counter, CCCR, and ESCR from Table
18-26.
5. Use the WRMSR instruction to write the ESCR Event Select and ESCR Event Mask
values into the appropriate fields in the ESCR. At the same time set or clear the
USR and OS flags in the ESCR as desired.
6. Use the WRMSR instruction to write the CCCR Select value into the appropriate
field in the CCCR.
NOTE
Typically all the fields and flags of the CCCR will be written with one
WRMSR instruction; however, in this procedure, several WRMSR
writes are used to more clearly demonstrate the uses of the various
CCCR fields and flags.
This setup procedure is continued in the next section, Section 18.18.6.2, “Filtering
Events.”
18.18.6.2 Filtering Events
Each counter receives up to 4 input lines from the processor hardware from which it
is counting events. The counter treats these inputs as binary inputs (input 0 has a
value of 1, input 1 has a value of 2, input 3 has a value of 4, and input 3 has a value
of 8). When a counter is enabled, it adds this binary input value to the counter value
on each clock cycle. For each clock cycle, the value added to the counter can then
range from 0 (no event) to 15.
For many events, only the 0 input line is active, so the counter is merely counting the
clock cycles during which the 0 input is asserted. However, for some events two or
more input lines are used. Here, the counters threshold setting can be used to filter