Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-108 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
18.18.6.3 Starting Event Counting
Event counting by a performance counter can be initiated in either of two ways. The
typical way is to set the enable flag in the counter’s CCCR. Following the instruction
to set the enable flag, event counting begins and continues until it is stopped (see
Section 18.18.6.5, “Halting Event Counting”).
The following procedural step shows how to start event counting. This step is a
continuation of the setup procedure introduced in Section 18.18.6.2, “Filtering
Events.”
9. To start event counting, use the WRMSR instruction to set the CCCR enable flag
for the performance counter.
This setup procedure is continued in the next section, Section 18.18.6.4, “Reading a
Performance Counter’s Count.”
The second way that a counter can be started by using the cascade feature. Here, the
overflow of one counter automatically starts its alternate counter (see Section
18.18.6.6, “Cascading Counters”).
18.18.6.4 Reading a Performance Counter’s Count
The Pentium 4 and Intel Xeon processors’ performance counters can be read using
either the RDPMC or RDMSR instructions. The enhanced functions of the RDPMC
instruction (including fast read) are described in Section 18.18.2, “Performance
Counters.” These instructions can be used to read a performance counter while it is
counting or when it is stopped.
The following procedural step shows how to read the event counter. This step is a
continuation of the setup procedure introduced in Section 18.18.6.3, “Starting Event
Counting.”
10. To read a performance counters current event count, execute the RDPMC
instruction with the counter number obtained from Table 18-26 used as an
operand.
Figure 18-44. Effects of Edge Filtering
Output from
Threshold Filter
Counter Increments
On Rising Edge
(False-to-True)
Processor Clock