Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-109
DEBUGGING AND PERFORMANCE MONITORING
This setup procedure is continued in the next section, Section 18.18.6.5, “Halting
Event Counting.”
18.18.6.5 Halting Event Counting
After a performance counter has been started (enabled), it continues counting indef-
initely. If the counter overflows (goes one count past its maximum count), it wraps
around and continues counting. When the counter wraps around, it sets its OVF flag
to indicate that the counter has overflowed. The OVF flag is a sticky flag that indi-
cates that the counter has overflowed at least once since the OVF bit was last
cleared.
To halt counting, the CCCR enable flag for the counter must be cleared.
The following procedural step shows how to stop event counting. This step is a
continuation of the setup procedure introduced in Section 18.18.6.4, “Reading a
Performance Counter’s Count.”
11. To stop event counting, execute a WRMSR instruction to clear the CCCR enable
flag for the performance counter.
To halt a cascaded counter (a counter that was started when its alternate counter
overflowed), either clear the Cascade flag in the cascaded counter’s CCCR MSR or
clear the OVF flag in the alternate counter’s CCCR MSR.
18.18.6.6 Cascading Counters
As described in Section 18.18.2, “Performance Counters,” eighteen performance
counters are implemented in pairs. Nine pairs of counters and associated CCCRs are
further organized as four blocks: BPU, MS, FLAME, and IQ (see Table 18-26). The first
three blocks contain two pairs each. The IQ block contains three pairs of counters (12
through 17) with associated CCCRs (MSR_IQ_CCCR0 through MSR_IQ_CCCR5).
The first 8 counter pairs (0 through 15) can be programmed using ESCRs to detect
performance monitoring events. Pairs of ESCRs in each of the four blocks allow many
different types of events to be counted. The cascade flag in the CCCR MSR allows
nested monitoring of events to be performed by cascading one counter to a second
counter located in another pair in the same block (see Figure 18-37 for the location
of the flag).
Counters 0 and 1 form the first pair in the BPU block. Either counter 0 or 1 can be
programmed to detect an event via MSR_MO B_ESCR0. Counters 0 and 2 can be
cascaded in any order, as can counters 1 and 3. It’s possible to set up 4 counters in
the same block to cascade on two pairs of independent events. The pairing described
also applies to subsequent blocks. Since the IQ PUB has two extra counters,
cascading operates somewhat differently if 16 and 17 are involved. In the IQ block,
counter 16 can only be cascaded from counter 14 (not from 12); counter 14 cannot
be cascaded from counter 16 using the CCCR cascade bit mechanism. Similar restric-
tions apply to counter 17.