Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-110 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
Example 18-1. Counting Events
Assume a scenario where counter X is set up to count 200 occurrences of event A;
then counter Y is set up to count 400 occurrences of event B. Each counter is set up
to count a specific event and overflow to the next counter. In the above example,
counter X is preset for a count of -200 and counter Y for a count of -400; this setup
causes the counters to overflow on the 200th and 400th counts respectively.
Continuing this scenario, counter X is set up to count indefinitely and wraparound on
overflow. This is described in the basic performance counter setup procedure that
begins in Section 18.18.6.1, “Selecting Events to Count.” Counter Y is set up with the
cascade flag in its associated CCCR MSR set to 1 and its enable flag set to 0.
To begin the nested counting, the enable bit for the counter X is set. Once enabled,
counter X counts until it overflows. At this point, counter Y is automatically enabled
and begins counting. Thus counter X overflows after 200 occurrences of event A.
Counter Y then starts, counting 400 occurrences of event B before overflowing. When
performance counters are cascaded, the counter Y would typically be set up to
generate an interrupt on overflow. This is described in Section 18.18.6.8, “Gener-
ating an Interrupt on Overflow.”
The cascading counters mechanism can be used to count a single event. The
counting begins on one counter then continues on the second counter after the first
counter overflows. This technique doubles the number of event counts that can be
recorded, since the contents of the two counters can be added together.
18.18.6.7 EXTENDED CASCADING
Extended cascading is a model-specific feature in the Intel NetBurst microarchitec-
ture. The feature is available to Pentium 4 and Xeon processor family with family
encoding of 15 and model encoding greater than or equal to 2. This feature uses bit
11 in CCCRs associated with the IQ block. See Table 18-28.
Table 18-28. CCR Names and Bit Positions
CCCR Name:Bit Position Bit Name Description
MSR_IQ_CCCR1|2:11 Reserved
MSR_IQ_CCCR0:11 CASCNT4INTO0 Allow counter 4 to cascade into
counter 0
MSR_IQ_CCCR3:11 CASCNT5INTO3 Allow counter 5 to cascade into
counter 3
MSR_IQ_CCCR4:11 CASCNT5INTO4 Allow counter 5 to cascade into
counter 4
MSR_IQ_CCCR5:11 CASCNT4INTO5 Allow counter 4 to cascade into
counter 5