Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-119
DEBUGGING AND PERFORMANCE MONITORING
The sections below describe performance counters, event qualification by logical
processor ID, and special purpose bits in ESCRs/CCCRs. They also describe
MSR_PEBS_ENABLE, MSR_PEBS_MATRIX_VERT, and MSR_TC_PRECISE_EVENT.
18.19.1 ESCR MSRs
Figure 18-45 shows the layout of an ESCR MSR in processors supporting Intel Hyper-
Threading Technology.
The functions of the flags and fields are as follows:
• T1_USR flag, bit 0 — When set, events are counted when thread 1 (logical
processor 1) is executing at a current privilege level (CPL) of 1, 2, or 3. These
privilege levels are generally used by application code and unprotected operating
system code.
• T1_OS flag, bit 1 — When set, events are counted when thread 1 (logical
processor 1) is executing at CPL of 0. This privilege level is generally reserved for
protected operating system code. (When both the T1_OS and T1_USR flags are
set, thread 1 events are counted at all privilege levels.)
• T0_USR flag, bit 2 — When set, events are counted when thread 0 (logical
processor 0) is executing at a CPL of 1, 2, or 3.
• T0_OS flag, bit 3 — When set, events are counted when thread 0 (logical
processor 0) is executing at CPL of 0. (When both the T0_OS and T0_USR flags
are set, thread 0 events are counted at all privilege levels.)
Figure 18-45. Event Selection Control Register (ESCR) for the Pentium 4 Processor,
Intel Xeon Processor and Intel Xeon Processor MP Supporting Hyper-Threading
Technology
31 24 8 0123492530
63
32
Reserved
Event Mask
Event
Select
T0_USR
T0_OS
5
Tag Enable
Tag
Value
T1_USR
T1_OS
Reserved