Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-120 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
• Tag enable, bit 4 — When set, enables tagging of μops to assist in at-retirement
event counting; when clear, disables tagging. See Section 18.18.7, “At-
Retirement Counting.”
• Tag value field, bits 5 through 8 — Selects a tag value to associate with a μop
to assist in at-retirement event counting.
• Event mask field, bits 9 through 24 — Selects events to be counted from the
event class selected with the event select field.
• Event select field, bits 25 through 30) — Selects a class of events to be
counted. The events within this class that are counted are selected with the event
mask field.
The T0_OS and T0_USR flags and the T1_OS and T1_USR flags allow event counting
and sampling to be specified for a specific logical processor (0 or 1) within an Intel
Xeon processor MP (See also: Section 7.5.5, “Identifying Logical Processors in an MP
System,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A).
Not all performance monitoring events can be detected within an Intel Xeon
processor MP on a per logical processor basis (see Section 18.19.4, “Performance
Monitoring Events”). Some sub-events (specified by an event mask bits) are counted
or sampled without regard to which logical processor is associated with the detected
event.
18.19.2 CCCR MSRs
Figure 18-46 shows the layout of a CCCR MSR in processors supporting Intel Hyper-
Threading Technology. The functions of the flags and fields are as follows:
• Enable flag, bit 12 — When set, enables counting; when clear, the counter is
disabled. This flag is cleared on reset
• ESCR select field, bits 13 through 15 — Identifies the ESCR to be used to
select events to be counted with the counter associated with the CCCR.
• Active thread field, bits 16 and 17 — Enables counting depending on which
logical processors are active (executing a thread). This field enables filtering of
events based on the state (active or inactive) of the logical processors. The
encodings of this field are as follows:
00 — None. Count only when neither logical processor is active.
01 — Single. Count only when one logical processor is active (either 0 or 1).
10 — Both. Count only when both logical processors are active.
11 — Any. Count when either logical processor is active.
A halted logical processor or a logical processor in the “wait for SIPI” state is
considered inactive.