Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

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DEBUGGING AND PERFORMANCE MONITORING
• FORCE_OVF flag, bit 25 — When set, forces a counter overflow on every
counter increment; when clear, overflow only occurs when the counter actually
overflows.
• OVF_PMI_T0 flag, bit 26 — When set, causes a performance monitor interrupt
(PMI) to be sent to logical processor 0 when the counter overflows occurs; when
clear, disables PMI generation for logical processor 0. Note that the PMI is
generate on the next event count after the counter has overflowed.
• OVF_PMI_T1 flag, bit 27 — When set, causes a performance monitor interrupt
(PMI) to be sent to logical processor 1 when the counter overflows occurs; when
clear, disables PMI generation for logical processor 1. Note that the PMI is
generate on the next event count after the counter has overflowed.
• Cascade flag, bit 30 — When set, enables counting on one counter of a counter
pair when its alternate counter in the other the counter pair in the same counter
group overflows (see Section 18.18.2, “Performance Counters,” for further
details); when clear, disables cascading of counters.
• OVF flag, bit 31 — Indicates that the counter has overflowed when set. This flag
is a sticky flag that must be explicitly cleared by software.
18.19.3 IA32_PEBS_ENABLE MSR
In a processor supporting Intel Hyper-Threading Technology and based on the Intel
NetBurst microarchitecture, PEBS is enabled and qualified with two bits in the
MSR_PEBS_ENABLE MSR: bit 25 (ENABLE_PEBS_MY_THR) and 26
(ENABLE_PEBS_OTH_THR) respectively. These bits do not explicitly identify a
specific logical processor by logic processor ID(T0 or T1); instead, they allow a soft-
ware agent to enable PEBS for subsequent threads of execution on the same logical
processor on which the agent is running (“my thread”) or for the other logical
processor in the physical package on which the agent is not running (“other thread”).
PEBS is supported for only a subset of the at-retirement events: Execution_event,
Front_end_event, and Replay_event. Also, PEBS can be carried out only with two
performance counters: MSR_IQ_CCCR4 (MSR address 370H) for logical processor 0
and MSR_IQ_CCCR5 (MSR address 371H) for logical processor 1.
Performance monitoring tools should use a processor affinity mask to bind the kernel
mode components that need to modify the ENABLE_PEBS_MY_THR and
ENABLE_PEBS_OTH_THR bits in the MSR_PEBS_ENABLE MSR to a specific logical
processor. This is to prevent these kernel mode components from migrating between
different logical processors due to OS scheduling.
18.19.4 Performance Monitoring Events
All of the events listed in Table A-9 and A-10 are available in an Intel Xeon processor
MP. When Intel Hyper-Threading Technology is active, many performance monitoring
events can be can be qualified by the logical processor ID, which corresponds to bit 0