Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

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DEBUGGING AND PERFORMANCE MONITORING
2. Select an appropriate counter.
3. Enable counting in the CCCR for that counter by setting the enable bit.
18.20.2 Non-Sleep Clockticks
Performance monitoring counters can be configured to count clockticks whenever the
performance monitoring hardware is not powered-down. To count Non-sleep Clock-
ticks with a performance-monitoring counter, do the following:
1. Select one of the 18 counters.
2. Select any of the ESCRs whose events the selected counter can count. Set its
event select to anything other than no_event. This may not seem necessary, but
the counter may be disabled if this is not done.
3. Turn threshold comparison on in the CCCR by setting the compare bit to 1.
4. Set the threshold to 15 and the complement to 1 in the CCCR. Since no event can
exceed this threshold, the threshold condition is met every cycle and the counter
counts every cycle. Note that this overrides any qualification (e.g. by CPL)
specified in the ESCR.
5. Enable counting in the CCCR for the counter by setting the enable bit.
In most cases, the counts produced by the non-halted and non-sleep metrics are
equivalent if the physical package supports one logical processor and is not placed in
a power-saving state. Operating systems may execute an HLT instruction and place a
physical processor in a power-saving state.
On processors that support Intel Hyper-Threading Technology (Intel HT Technology),
each physical package can support two or more logical processors. Current imple-
mentation of Intel HT Technology provides two logical processors for each physical
processor. While both logical processors can execute two threads simultaneously,
one logical processor may halt to allow the other logical processor to execute without
sharing execution resources between two logical processors.
Non-halted Clockticks can be set up to count the number of processor clock cycles for
each logical processor whenever the logical processor is not halted (the count may
include some portion of the clock cycles for that logical processor to complete a tran-
sition to a halted state). Physical processors that support Intel HT Technology enter
into a power-saving state if all logical processors halt.
The Non-sleep Clockticks mechanism uses a filtering mechanism in CCCRs. The
mechanism will continue to increment as long as one logical processor is not halted
or in a power-saving state. Applications may cause a processor to enter into a power-
saving state by using an OS service that transfers control to an OS’s idle loop. The
idle loop then may place the processor into a power-saving state after an implemen-
tation-dependent period if there is no work for the processor.