Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

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DEBUGGING AND PERFORMANCE MONITORING
18.24 PERFORMANCE MONITORING ON L3 AND CACHING
BUS CONTROLLER SUB-SYSTEMS
The Intel Xeon processor 7400 series and Dual-Core Intel Xeon processor 7100
series employ a distinct L3/caching bus controller sub-system. These sub-system
have a unique set of performance monitoring capability and programming interfaces
that are largely common between these two processor families.
Intel Xeon processor 7400 series are based on 45nm enhanced Intel Core microar-
chitecture. The CPUID signature is indicated by DisplayFamily_DisplayModel value of
06_1DH. Intel Xeon processor 7400 series have six processor cores that share an L3
cache.
Dual-Core Intel Xeon processor 7100 series are based on Intel NetBurst microarchi-
tecture, have a CPUID signature of family [0FH], model [06H] and a unified L3 cache
shared between two cores. Each core in an Intel Xeon processor 7100 series supports
Intel Hyper-Threading Technology, providing two logical processors per core.
Both Intel Xeon processor 7400 series and Intel Xeon processor 7100 series support
multi-processor configurations using system bus interfaces. In Intel Xeon processor
7400 series, the L3/caching bus controller sub-system provides three Simple Direct
Interface (SDI) to service transactions originated the XQ-replacement SDI logic in
each dual-core modules. In Intel Xeon processor 7100 series, the IOQ logic in each
processor core is replaced with a Simple Direct Interface (SDI) logic. The L3 cache is
connected between the system bus and the SDI through additional control logic. See
Figure 18-52. MSR_IFSB_CTL6, Address: 107D2H;
MSR_IFSB_CNTR7, Address: 107D3H
Reserved
MSR_IFSB_CTL6 Address: 107D2H
MSR_IFSB_CNTR7 Address: 107D3H
Enable
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0
5759
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64 bit event count