Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-137
DEBUGGING AND PERFORMANCE MONITORING
• Four MSRs (MSR_EMON_L3_CTR_CTL4, MSR_EMON_L3_CTR_CTL5,
MSR_EMON_L3_CTR_CTL6, and MSR_EMON_L3_CTR_CTL7) are dedicated to
counting external bus operations.
The bit fields in each of eight MSRs share the following common characteristics:
• Bits 63:32 is the event control field that includes an event mask and other bit
fields that control counter operation. The event mask field specifies details of the
microarchitectural condition, and its definition differs across GBSQ, GSNPQ, FSB.
• Bits 31:0 is the event count field. If the specified condition is met during each
relevant clock domain of the event logic, the matched condition signals the
counter logic to increment the associated event count field. The lower 32-bits of
these 8 MSRs at addresses 107CC through 107D3 are treated as 32 bit
performance counter registers.
These performance counters can be accessed using RDPMC instruction with the index
starting from 18 through 25. The EDX register returns zero when reading these 8
PMCs.
18.24.2 GBSQ Event Interface
The layout of MSR_EMON_L3_CTR_CTL0 and MSR_EMON_L3_CTR_CTL1 is given in
Figure 18-55. Counting starts after software writes a non-zero value to one or more
of the upper 32 bits.
The event mask field (bits 58:32) consists of the following eight attributes:
• Agent_Select (bits 35:32): The definition of this field differs slightly between
Intel Xeon processor 7100 and 7400.
For Intel Xeon processor 7100 series, each bit specifies a logical processor in the
physical package. The lower two bits corresponds to two logical processors in the
first processor core, the upper two bits corresponds to two logical processors in
the second processor core. 0FH encoding matches transactions from any logical
processor.
For Intel Xeon processor 7400 series, each bit of [34:32] specifies the SDI logic
of a dual-core module as the originator of the transaction. A value of 0111B in
bits [35:32] specifies transaction from any processor core.