Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-144 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
measure duration. When counting events, a counter increments each time a speci-
fied event takes place or a specified number of events takes place. When measuring
duration, it counts the number of processor clocks that occur while a specified condi-
tion is true. The counters can count events or measure durations that occur at any
privilege level.
Table A-18, Appendix A, lists the events that can be counted with the P6 family
performance monitoring counters.
NOTE
The performance-monitoring events listed in Appendix A are
intended to be used as guides for performance tuning. Counter
values reported are not guaranteed to be accurate and should be
used as a relative guide for tuning. Known discrepancies are
documented where applicable.
The performance-monitoring counters are supported by four MSRs: the performance
event select MSRs (PerfEvtSel0 and PerfEvtSel1) and the performance counter MSRs
(PerfCtr0 and PerfCtr1). These registers can be read from and written to using the
RDMSR and WRMSR instructions, respectively. They can be accessed using these
instructions only when operating at privilege level 0. The PerfCtr0 and PerfCtr1 MSRs
can be read from any privilege level using the RDPMC (read performance-monitoring
counters) instruction.
NOTE
The PerfEvtSel0, PerfEvtSel1, PerfCtr0, and PerfCtr1 MSRs and the
events listed in Table A-18 are model-specific for P6 family
processors. They are not guaranteed to be available in other IA-32
processors.
18.25.1 PerfEvtSel0 and PerfEvtSel1 MSRs
The PerfEvtSel0 and PerfEvtSel1 MSRs control the operation of the performance-
monitoring counters, with one register used to set up each counter. They specify the
events to be counted, how they should be counted, and the privilege levels at which
counting should take place. Figure 18-58 shows the flags and fields in these MSRs.
The functions of the flags and fields in the PerfEvtSel0 and PerfEvtSel1 MSRs are as
follows:
• Event select field (bits 0 through 7) — Selects the event logic unit to detect
certain microarchitectural conditions (see Table A-18, for a list of events and their
8-bit codes).
• Unit mask (UMASK) field (bits 8 through 15) — Further qualifies the event
logic unit selected in the event select field to detect a specific microarchitectural
condition. For example, for some cache events, the mask is used as a MESI-
protocol qualifier of cache states (see Table A-18).