Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-149
DEBUGGING AND PERFORMANCE MONITORING
• CC0 and CC1 (counter control) fields (bits 6-8, bits 22-24) — Controls the
operation of the counter. Control codes are as follows:
000 — Count nothing (counter disabled)
001 — Count the selected event while CPL is 0, 1, or 2
010 — Count the selected event while CPL is 3
011 — Count the selected event regardless of CPL
100 — Count nothing (counter disabled)
101 — Count clocks (duration) while CPL is 0, 1, or 2
110 — Count clocks (duration) while CPL is 3
111 — Count clocks (duration) regardless of CPL
The highest order bit selects between counting events and counting clocks
(duration); the middle bit enables counting when the CPL is 3; and the low-order
bit enables counting when the CPL is 0, 1, or 2.
• PC0 and PC1 (pin control) flags (bits 9, 25) — Selects the function of the
external performance-monitoring counter pin (PM0/BP0 and PM1/BP1). Setting
one of these flags to 1 causes the processor to assert its associated pin when the
counter has overflowed; setting the flag to 0 causes the pin to be asserted when
the counter has been incremented. These flags permit the pins to be individually
programmed to indicate the overflow or incremented condition. The external
signalling of the event on the pins will lag the internal event by a few clocks as the
signals are latched and buffered.
While a counter need not be stopped to sample its contents, it must be stopped and
cleared or preset before switching to a new event. It is not possible to set one
counter separately. If only one event needs to be changed, the CESR register must
Figure 18-59. CESR MSR (Pentium Processor Only)
31
PC1—Pin control 1
CC1—Counter control 1
ES1—Event select 1
PC0—Pin control 0
8
0
CC0—Counter control 0
ES0—Event select 0
16 152122
24
Reserved
9
5
6
ESOCC0
P
C
0
ES1
CC1
P
C
1
2526
10