Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 20-15
VIRTUAL-MACHINE CONTROL STRUCTURES
and two 32-bit fields in the VMCS (the page-fault error-code mask and page-
fault error-code match). See Section 21.3 for details.
20.6.4 I/O-Bitmap Addresses
The VM-execution control fields include the 64-bit physical addresses of I/O
bitmaps A and B (each of which are 4 KBytes in size). I/O bitmap A contains one bit
for each I/O port in the range 0000H through 7FFFH; I/O bitmap B contains bits for
ports in the range 8000H through FFFFH.
A logical processor uses these bitmaps if and only if the “use I/O bitmaps” control is
1. If the bitmaps are used, execution of an I/O instruction causes a VM exit if any bit
in the I/O bitmaps corresponding to a port it accesses is 1. See Section 21.1.3 for
details. If the bitmaps are used, their addresses must be 4-KByte aligned.
20.6.5 Time-Stamp Counter Offset
VM-execution control fields include a 64-bit TSC-offset field. If the “RDTSC exiting”
control is 0 and the “use TSC offsetting” control is 1, this field controls executions of
the RDTSC and RDTSCP instructions. It also controls executions of the RDMSR
instruction that read from the IA32_TIME_STAMP_COUNTER MSR. For all of these,
the signed value of the TSC offset is combined with the contents of the time-stamp
counter (using signed addition) and the sum is reported to guest software in
EDX:EAX. See Chapter 21 for a detailed treatment of the behavior of RDTSC,
RDTSCP, and RDMSR in VMX non-root operation.
20.6.6 Guest/Host Masks and Read Shadows for CR0 and CR4
VM-execution control fields include guest/host masks and read shadows for the
CR0 and CR4 registers. These fields control executions of instructions that access
those registers (including CLTS, LMSW, MOV CR, and SMSW). They are 64 bits on
processors that support Intel 64 architecture and 32 bits on processors that do not.
In general, bits set to 1 in a guest/host mask correspond to bits “owned” by the host:
• Guest attempts to set them (using CLTS, LMSW, or MOV to CR) to values differing
from the corresponding bits in the corresponding read shadow cause VM exits.
• Guest reads (using MOV from CR or SMSW) return values for these bits from the
corresponding read shadow.
Bits cleared to 0 correspond to bits “owned” by the guest; guest attempts to modify
them succeed and guest reads return values for these bits from the control register
itself.
See Chapter 21 for details regarding how these fields affect VMX non-root operation.