Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 21-3
VMX NON-ROOT OPERATION
21.1.3 Instructions That Cause VM Exits Conditionally
Certain instructions cause VM exits in VMX non-root operation depending on the
setting of the VM-execution controls. The following instructions can cause “fault-like”
VM exits based on the conditions described:
• CLTS. The CLTS instruction causes a VM exit if the bits in position 3 (corre-
sponding to CR0.TS) are set in both the CR0 guest/host mask and the CR0 read
shadow.
• HLT. The HLT instruction causes a VM exit if the “HLT exiting” VM-execution
control is 1.
• IN, INS/INSB/INSW/INSD, OUT, OUTS/OUTSB/OUTSW/OUTSD. The
behavior of each of these instructions is determined by the settings of the
“unconditional I/O exiting” and “use I/O bitmaps” VM-execution controls:
— If both controls are 0, the instruction executes normally.
— If the “unconditional I/O exiting” VM-execution control is 1 and the “use I/O
bitmaps” VM-execution control is 0, the instruction causes a VM exit.
— If the “use I/O bitmaps” VM-execution control is 1, the instruction causes a
VM exit if it attempts to access an I/O port corresponding to a bit set to 1 in
the appropriate I/O bitmap (see Section 20.6.4). If an I/O operation “wraps
around” the 16-bit I/O-port space (accesses ports FFFFH and 0000H), the I/O
instruction causes a VM exit (the “unconditional I/O exiting” VM-execution
control is ignored if the “use I/O bitmaps” VM-execution control is 1).
See Section 21.1.1 for information regarding the priority of VM exits relative to
faults that may be caused by the INS and OUTS instructions.
• INLVPG. The INLVPG instruction causes a VM exit if the “INLVPG exiting”
VM-execution control is 1.
• LGDT, LIDT, LLDT, LTR, SGDT, SIDT, SLDT, STR. These instructions cause
VM exits if the “descriptor-table exiting” VM-execution control is 1.
1
• LMSW. In general, the LMSW instruction causes a VM exit if it would write, for
any bit set in the low 4 bits of the CR0 guest/host mask, a value different than the
corresponding bit in the CR0 read shadow. Note that LMSW never clears bit 0 of
CR0 (CR0.PE). Thus, LMSW causes a VM exit if either of the following are true:
— The bits in position 0 (corresponding to CR0.PE) are set in both the CR0
guest/mask and the source operand, and the bit in position 0 is clear in the
CR0 read shadow.
— For any bit position in the range 3:1, the bit in that position is set in the CR0
guest/mask and the values of the corresponding bits in the source operand
and the CR0 read shadow differ.
1. Note that “descriptor-table exiting” is a secondary processor-based VM-execution control. If
bit 31 of the primary processor-based VM-execution controls is 0, VMX non-root operation func-
tions as if the “descriptor-table exiting” VM-execution control were 0. See Section 20.6.2.