Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

21-6 Vol. 3
VMX NON-ROOT OPERATION
updated by the instruction (for example, the value of CS:RIP saved in the guest-state
area of the VMCS references the next instruction).
Specifically, a trap-like VM exit occurs following either instruction if the execution
reduces the value of the TPR shadow below that of the TPR threshold VM-execution
control field (see Section 20.6.8 and Section 21.4) and the following hold:
• For MOV to CR8:
— The “CR8-load exiting” VM-execution control is 0.
— The “use TPR shadow” VM-execution control is 1.
• For WRMSR:
— The “use MSR bitmaps” VM-execution control is 1, the value of ECX is 808H,
and bit 808H in write bitmap for low MSRs is 0 (see above).
— The “virtualize x2APIC mode” VM-execution control is 1.
21.2 APIC-ACCESS VM EXITS
If the “virtualize APIC accesses” VM-execution control is 1, an attempt to access
memory using a physical address on the APIC-access page (see Section 20.6.8)
causes a VM exit.
1,2
Such a VM exit is called an APIC-access VM exit.
Whether an operation that attempts to access memory with a physical address on the
APIC-access page causes an APIC-access VM exit may be qualified based on the type
of access. Section 21.2.1 describes the treatment of linear accesses, while Section
21.2.3 describes that of physical accesses. Section 21.2.4 discusses accesses to the
TPR field on the APIC-access page (called VTPR accesses), which do not, if the “use
TPR shadow” VM-execution control is 1, cause APIC-access VM exits.
21.2.1 Linear Accesses to the APIC-Access Page
An access to the APIC-access page is called a linear access if (1) it results from a
memory access using a linear address; and (2) the access’s physical address is the
translation of that linear address. Section 21.2.1.1 specifies which linear accesses to
the APIC-access page cause APIC-access VM exits.
3. Note that “virtualize x2APIC mode” is a secondary processor-based VM-execution control. If
bit 31 of the primary processor-based VM-execution controls is 0, VMX non-root operation func-
tions as if the “virtualize x2APIC mode” VM-execution control were 0. See Section 20.6.2.
1. Note that “virtualize APIC accesses” is a secondary processor-based VM-execution control. If
bit 31 of the primary processor-based VM-execution controls is 0, VMX non-root operation func-
tions as if the “virtualize APIC accesses” VM-execution control were 0. See Section 20.6.2.
2. Even when addresses are translated using EPT (see Chapter 24), the determination of whether
an APIC-access VM exit occurs depends on an access’s physical address, not its guest-physical
address.