Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 21-7
VMX NON-ROOT OPERATION
In general, the treatment of APIC-access VM exits caused by linear accesses is
similar to that of page faults and EPT violations. Based upon this treatment, Section
21.2.1.2 specifies the priority of such VM exits with respect to other events, while
Section 21.2.1.3 discusses instructions that may cause page faults without accessing
memory and the treatment when they access the APIC-access page.
21.2.1.1 Linear Accesses That Cause APIC-Access VM Exits
Whether a linear access to the APIC-access page causes an APIC-access VM exit
depends in part of the nature of the translation used by the linear address:
• If the linear access uses a translation with a 4-KByte page, it causes an APIC-
access VM exit.
• If the linear access uses a translation with a large page (2-MByte or 4-MByte),
the access may or may not cause an APIC-access VM exit. Section 21.5.1
describes the treatment of such accesses that do not cause an APIC-access
VM exits.
If EPT is in use, a linear access uses a translation with a large page only if a
large page is specified by both the guest paging structures and the EPT paging
structures.
It is recommended that software configure the paging structures so that any transla-
tion to the APIC-access page uses a 4-KByte page.
A linear access to the APIC-access page might not cause an APIC-access VM exit if
the “enable EPT” VM-execution control is 1 and software has not properly invalidate
information cached from the EPT paging structures:
• At time t
1
, EPT was in use, the EPTP value was X, and some guest-physical
address Y translated to an address that was not on the APIC-access page at that
time. (This might be because the “virtualize APIC accesses” VM-execution control
was 0.)
• At later time t
2
, EPT is in use, the EPTP value is X, and a memory access uses a
linear address that translates to Y, which now translates to an address on the
APIC-access page. (This implies that the “virtualize APIC accesses” VM-execution
control is 1 at this time.)
• Software did not execute the INVEPT instruction between times t
1
and t
2
, either
with the all-context INVEPT type or with the single-context INVEPT type and X as
the INVEPT descriptor.
In this case, the linear access at time t
2
might or might not cause an APIC-access
VM exit. If it does not, the access operates on memory on the APIC-access page.
Software can avoid this situation through appropriate use of the INVEPT instruction;
see Section 24.3.3.4.
A linear access to the APIC-access page might not cause an APIC-access VM exit if
the “enable VPID” VM-execution control is 1 and software has not properly invali-
dated the TLBs and paging-structure caches: