Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

21-8 Vol. 3
VMX NON-ROOT OPERATION
• At time t
1
, the processor was in VMX non-root operation with non-zero VPID X,
and some linear address Y translated to an address that was not on the APIC-
access page at that time. (This might be because the “virtualize APIC accesses”
VM-execution control was 0.)
• At later time t
2
, the processor was again in VMX non-root operation with VPID X,
and a memory access uses linear address, which now translates to an address on
the APIC-access page. (This implies that the “virtualize APIC accesses” VM-
execution control is 1 at this time.)
• Software did not execute the INVVPID instruction in any of the following ways
between times t
1
and t
2
:
— With the individual-address INVVPID type and an INVVPID descriptor
specifying VPID X and linear address Y.
— With the single-context INVVPID type and an INVVPID descriptor specifying
VPID X.
— With the all-context INVEPT type.
— With the single-context-retaining-globals INVVPID type and an INVVPID
descriptor specifying VPID X (assuming that, at time t1, the translation for Y
was global; see Section 3.12, “Translation Lookaside Buffers (TLBs)” in
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A
for details regarding global translations).
In this case, the linear access at time t
2
might or might not cause an APIC-access
VM exit. If it does not, the access operates on memory on the APIC-access page.
Software can avoid this situation through appropriate use of the INVVPID instruction;
see Section 24.3.3.3.
21.2.1.2 Priority of APIC-Access VM Exits Caused by Linear Accesses
The following items specify the priority relative to other events of APIC-access
VM exits caused by linear accesses.
• The priority of an APIC-access VM exit on a linear access to memory is below that
of any page fault or EPT violation that that access may incur. That is, a linear
access does not cause an APIC-access VM exit if it would cause a page fault or an
EPT violation.
• A linear access does not cause an APIC-access VM exit until after the accessed
bits are set in the paging structures.
• A linear write access will not cause an APIC-access VM exit until after the dirty bit
is set in the appropriate paging structure.
• With respect to all other events, any APIC-access VM exit due to a linear access
has the same priority as any page fault or EPT violation that the linear access
could cause. (This item applies to other events that the linear access may
generate as well as events that may be generated by other accesses by the same
instruction or operation.)